xref: /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala (revision 86d9c530f01ccb7b492813b969b2d3fc7236b0c9)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import chisel3.experimental.chiselName
23import xiangshan._
24import utils._
25
26@chiselName
27class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst with HasPerfEvents {
28  val (components, resp) = getBPDComponents(io.in.bits.resp_in(0), p)
29  io.out.resp := resp
30
31  var metas = 0.U(1.W)
32  var meta_sz = 0
33  for (c <- components) {
34    c.io.in.valid            := io.in.valid
35    c.io.in.bits.s0_pc       := io.in.bits.s0_pc
36    c.io.in.bits.folded_hist := io.in.bits.folded_hist
37    c.io.in.bits.ghist       := io.in.bits.ghist
38
39    c.io.s0_fire := io.s0_fire
40    c.io.s1_fire := io.s1_fire
41    c.io.s2_fire := io.s2_fire
42
43    c.io.redirect := io.redirect
44
45    if (c.meta_size > 0) {
46      metas = (metas << c.meta_size) | c.io.out.last_stage_meta(c.meta_size-1,0)
47    }
48    meta_sz = meta_sz + c.meta_size
49  }
50  println(s"total meta size: $meta_sz\n\n")
51
52  io.in.ready := components.map(_.io.s1_ready).reduce(_ && _)
53
54  io.s1_ready := components.map(_.io.s1_ready).reduce(_ && _)
55  io.s2_ready := components.map(_.io.s2_ready).reduce(_ && _)
56
57  require(meta_sz < MaxMetaLength)
58  io.out.last_stage_meta := metas
59
60  var update_meta = io.update.bits.meta
61  for (c <- components.reverse) {
62    c.io.update := io.update
63    c.io.update.bits.meta := update_meta
64    update_meta = update_meta >> c.meta_size
65  }
66
67  def extractMeta(meta: UInt, idx: Int): UInt = {
68    var update_meta = meta
69    var metas: Seq[UInt] = Nil
70    for (c <- components.reverse) {
71      metas = metas :+ update_meta
72      update_meta = update_meta >> c.meta_size
73    }
74    metas(idx)
75  }
76
77  override def getFoldedHistoryInfo = Some(components.map(_.getFoldedHistoryInfo.getOrElse(Set())).reduce(_++_))
78
79  val comp_1_perf = components(1).asInstanceOf[MicroBTB].getPerfEvents
80  val comp_2_perf = components(2).asInstanceOf[Tage_SC].getPerfEvents
81  val comp_3_perf = components(3).asInstanceOf[FTB].getPerfEvents
82  val perfEvents = comp_1_perf ++ comp_2_perf ++ comp_3_perf
83  generatePerfEvent()
84}
85