bpu: timing optimizations

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMux

bpu: timing optimizations

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

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BPU: Move reset physical priority to 1

BPU: Implement PhyPriorityMuxGenerator, distinguish between logical priority and physical priority

bpu: code clean ups, remove previous ghr impl

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

bpu: use circular buffer as global history register, and

* use compressed info to do redirects
* implement folded history class

Merge branch 'master' into ftb-tail-shared

add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

Merge branch 'master' into decoupled-frontend

Instr uncache: support instruction fecth from MMIO device ( flash ) (#1151)

* InstrUncache: change into 1 instruciton logic

* Frontend: add MMIO fetch port

* IFU: flush pipeline and only pass

Instr uncache: support instruction fecth from MMIO device ( flash ) (#1151)

* InstrUncache: change into 1 instruciton logic

* Frontend: add MMIO fetch port

* IFU: flush pipeline and only pass 1 instruction to backend when
finding the address is mmio

* BPU: set the resetVector to 10000000

* Frontend: connect ifu.uncache to instrUncache

* IFU: Fix conflict with master

* IFU: fix mmio instruction prediction problem

* IFU: fix tlb af only hold 1 cycle

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ftq: add performance counters for mispredicts and corrects from each

bp stage of each cfi type

frontend: let br/jmp share the last slot of an ftb entry, ghist update timing optimization

frontend: fix parameterization issue

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

frontend: code clean ups

frontend: remove deprecated code

Merge branch 'master' into merge-master

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

[WIP]BPU: Modified some interface definitions

[WIP]BPU: Decoupled frontend BPU design

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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ras: partly handle stack overflow problems (#748)

* ras: partly handle stack overflow problems

* ras: add overflow and underflow statistics

btb: use single port sram to meet timing constraints (#692)

* add perf counters for btb and ubtb
* update btb only on not hit or jalr mispredicts to reduce write stalls

Merge pull request #614 from RISCVERS/ubtb-alloc-on-write

do way-allocating while writing ubtb, thus preventing multiple hits