BPU: move target comparision before takenMask selection (#2324)

* bpu(timing): move s2_redirect targetDiff comparison

usually target is generated quicker than taken, so we do
targetDiff comparis

BPU: move target comparision before takenMask selection (#2324)

* bpu(timing): move s2_redirect targetDiff comparison

usually target is generated quicker than taken, so we do
targetDiff comparision before select by taken

* bpu: fix typo

* bpu: fix Scala compile

use object instead of naked function

* bpu: fix takenMask source error

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chore: remove deprecated brackets, APIs, etc. (#2321)

New RAS design (#2292)

By introducing non-volatile queue for specutive states, RAS avoids entry pollution

Co-authored-by: Easton Man <[email protected]>

add redirect latency stats, and use histogram for some old stats (#2299)

* add redirect latency stats, and use histogram for some old stats

* BPU: fix redirect logic

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Co-authored-b

add redirect latency stats, and use histogram for some old stats (#2299)

* add redirect latency stats, and use histogram for some old stats

* BPU: fix redirect logic

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Co-authored-by: Guokai Chen <[email protected]>

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bpu: duplicate most possible signal related to npc generation to address (#2254)

high fanout problems

Co-authored-by: Lingrui98 <[email protected]>

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

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Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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bpu: history checker switch and code style

bpu: use warn instead of error when checker disagree

bpu: add br_committed to update data path

bpu: fix checker history maintainence in various condition

bpu: fix history shift source

bpu: impl a history checker

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

bpu: bypass uftb prediction directly to composer to avoid potential long wires

bpu: do info calculation at s1 when generating s2_redirect

bpu: remove minimal pred and old ubtb

bpu: implement fully-associated micro ftb to replace current ubtb

bpu: refactor prediction i/o bundles

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

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bpu: reduce meta sram size

bpu: dealy s0_fire for one cycle

bpu, ftb, ftq: timing optimizations

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

fix for chipsalliance/chisel3#2496 (#1563)

pass reset vector from SimTop (#1545)