fix(MMU, RVH): correct the gpaddr computation in TLB (#3442)

fix(TLB): correct PPN response of bypass route for only VS stage (#3440)

Function `ptw_resp_bypass` chooses an incorrect PPN for TLB request
which only has VS Stage. It should choose ppn_s1 in this

fix(TLB): correct PPN response of bypass route for only VS stage (#3440)

Function `ptw_resp_bypass` chooses an incorrect PPN for TLB request
which only has VS Stage. It should choose ppn_s1 in this case. This
patch fixes this issue.

show more ...

PTW, RVH: fix the bug about unaligned check in isPf and isAf (#3428)

PTW, RVH: add the sv48 high gpaddr check (#3427)

PTW, RVH: init the A、D、PPN of fake pte to avoid wrong pf and wrong gpaddr in L1TLB (#3423)

1. init a、d、ppn of fake pte
2. modify the logic of isPf and isAf

PMA, MMU: Fix bug of PA48 (#3424)

*PMA: Extend the default memory space from 0x1000000000L to
0x1000000000000L
*MMU: only trigger accessfault when ppn above
PADDRBITS(48)-OFFSETBITS(12) is not ze

PMA, MMU: Fix bug of PA48 (#3424)

*PMA: Extend the default memory space from 0x1000000000L to
0x1000000000000L
*MMU: only trigger accessfault when ppn above
PADDRBITS(48)-OFFSETBITS(12) is not zero

show more ...

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
-

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
- bug fixes
- timing fixes
- SRAM-Queue | https://github.com/OpenXiangShan/CoupledL2/pull/228
- data SRAM splitted into 4 |
https://github.com/OpenXiangShan/CoupledL2/pull/229

---------

Co-authored-by: lixin <[email protected]>

show more ...

svpbmt: add simplified support (#3404)

Only the `pbmt` attribute is added and treated as MMIO when `pbmt` is NC
or IO.

---------

Co-authored-by: ngc7331 <[email protected]>

MMU, RVH: fix the refill of pte that has gpf and change the check of pf/gpf in PTW and HPTW (#3420)

1. gpf pte shouldn't be refilled in page cache
2. In stage2, U bit should be valid when pte is le

MMU, RVH: fix the refill of pte that has gpf and change the check of pf/gpf in PTW and HPTW (#3420)

1. gpf pte shouldn't be refilled in page cache
2. In stage2, U bit should be valid when pte is leaf
3. rewrite the check of pf and gpf in PTW and HPTW

show more ...

MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

L1TLB, RVH: fix the wrong gpf because checking s2 when ptw resp is onlystage1 (#3385)

PTW, RVH: fix the x state of stage1 pf/af when the first s2xlate happens gpf in PTW (#3357)

When the first s2xlate happens gpf, the pte is invalid, which makes the
pf and af of stage1 is x-states.

MMU, RVH, fix the af refill error when refilling page cache (#3331)

LLPTW, RVH: fix the bug that llptw resp wrong stage1 when first s2xlate has gpf in LLPTW (#3343)

llptw_stage1 stores the result from page cache for the gpf from the
first s2xlate in llptw. LLPTW ha

LLPTW, RVH: fix the bug that llptw resp wrong stage1 when first s2xlate has gpf in LLPTW (#3343)

llptw_stage1 stores the result from page cache for the gpf from the
first s2xlate in llptw. LLPTW has many entries, so llptw_stage1 need to
add some entries in L2TLB.

show more ...

PTW, RVH: fix the error S1 resp when gpf happened and s1_level == 0 (#3342)

When the resp is allstage and level == 0, PTW find pte and then gpf
happens in the last s2xlate before resp to l1tlb. We

PTW, RVH: fix the error S1 resp when gpf happened and s1_level == 0 (#3342)

When the resp is allstage and level == 0, PTW find pte and then gpf
happens in the last s2xlate before resp to l1tlb. We can't give fake pte
to stage1 because the pte that mem resp is valid in PTW.

show more ...

PTW, RVH: rewrite the PTW resp logic when PTW get gpf or gaf from HPTW

DCache: Block conflicting replacement for whole mshr lifecycle

DCache: Replay refill_req when the evict_addr matching a valid mshr

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

show more ...

TLB: adjust query logic

Dcache: refactor dcache's read data delay for better port timing

wpu: fix the issue of abnormal power (#2976)

fix points:
1. parameter bug in DCacheWrapper
2. add clock gate to avoid frequent flip in BankedDataArray
3. remove redundant designs in WPU

power

wpu: fix the issue of abnormal power (#2976)

fix points:
1. parameter bug in DCacheWrapper
2. add clock gate to avoid frequent flip in BankedDataArray
3. remove redundant designs in WPU

power comparison：

show more ...

PageCache, RVH: delete some comments

PageCache, RVH: add the condition that page cache resp L1tlb when stage1 hit but has pf in allstage