fix(xtval): fix xtval when raise intr (#4307)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags,

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags, fcsr,
* vxsat, vcsr, vstart,
* mstatus, sstatus, hstatus, vsstatus, mnstatus,
* dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
by Use-Level instruction without any fence, and executing OoO would
get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
need to let reading PMC CSRs inorder.

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fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>

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fix(Mcontrol6): fix writing mcontrol6.dmode for trigger chain (#4256)

refactor(MemBlock): move MemBlock.scala from backend to mem (#4221)

fix(vfalu): fix bug of allFFlagsEn when lastUop is reduction unorder sum (#4244)

fix(csr, difftest): distinguish external interrupts sources from PLIC or IMSIC

fix(csr): external interrupt priority from PLIC or IMSIC

fix(aia): iprio array is masked by xie CSR

* For a given interrupt number, if the corresponding bit in mie
is read-only zero, then the interrupt’s priority number in the
iprio array must be read

fix(aia): iprio array is masked by xie CSR

* For a given interrupt number, if the corresponding bit in mie
is read-only zero, then the interrupt’s priority number in the
iprio array must be read-only zero as well.

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feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop

feat(Zawrs): support Zawrs extension (#4211)

This commit implements a basic nop-based Zawrs extension.

- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1

Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.

Also, like WFI, interrupts cannot take on wrs instructions.

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submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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fix(vfalu): fix bug of outIsFisrtGroup when lmul=8 sew=16 uopidx>7 (#4201)

fix(dret): clear xstatus.xDT conditionally when dret is executed (#4193)

fix(mnret): add the missing mnret output connection (#4194)

feat(difftest): sync hgeip by difftest

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to acce

fix(aia): add the missing AIA-related permission checks

Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external
interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction
exception, and attempts from VS-mode to access stopei raise a virtual instruction exception.

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fix(VFALU): fix bug of f16FirstFoldMaskUnorder when fold to 1/2 (#4181)

feat(custom, csr): add two custom CSRs mcorepwr and mflushpwr to control power (#4164)

Co-authored-by: Zhu Yu <[email protected]>

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handl

feat(exception): divide the exceptions raised from CSR access into different sources (#4146)

Before this, we assumed that all possible exceptions during CSR read and
write operations should be handled according to their priority.

Therefore, we ensured that all illegal instruction exceptions take
precedence over virtual instruction exceptions.

However, with the implementation of certain extensions like Smcsrind and
Smstateen, we encounter scenarios where virtual instruction exceptions
must take precedence over illegal instruction exceptions triggered.

For instance, when mstateen0.csrind is set to 1 and hstateen0.csrind is
0, a virtual instruction exception should be raised if VS mode attempts
to access sireg. However, if the vsiselect value is reserved in this
situation, an illegal instruction exception will be raised instead. If
these checks are treated as being at the same priority level, an illegal
instruction exception would ultimately be raised.

In reality, a virtual instruction exception should take precedence
because when the extension is disabled, we should not even evaluate the
value of vsiselect.

Therefore, we divided the sources of exceptions caused by CSR access
into several categories: M-level, S-level, privilege level,
virtualization level, and indirect access level.

Among them, M-level and S-level will only raise illegal instruction
exceptions, the privilege level will raise both illegal instruction and
virtual instruction exceptions, the virtualization level will raise
virtual instruction exceptions, and indirect access will raise both
illegal instruction and virtual instruction exceptions. Therefore, we
handle the exceptions from the previous levels in the same way, and only
check for exceptions caused by indirect access after ensuring that no
exceptions were raised earlier.

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fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is upda

fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is updated when:
* time.valid of clint
* vstimecmp CSR is written
* htimedelta CSR is written
* menvcfg CSR is written
* henvcfg CSR is written

Co-authored-by: Xuan Hu <[email protected]>

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feat(CSR): set init 0 for htimedelta csr (#4145)

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mide

fix(hideleg): fix the read value of the LCOFI bit of hideleg.

For bits of mideleg that are zero, the corresponding bits in
hideleg, hip, and hie are read-only zeros.

The VSSIP, VSTIP, VSEIP in mideleg are read-only ones
when the H extension is implemented.

When the hypervisor extension is implemented, if a bit is zero in
the same position in both mideleg and mvien, then that bit is
read-only zero in hideleg (in addition to being read-only zero in
sip, sie, hip, and hie). But if a bit for one of interrupts 13-63
is a one in either mideleg or mvien, then the same bit in hideleg
may be writable or may be read-only zero, depending on the
implementation. No bits in hideleg are ever read-only ones. The
RISC-V Privileged Architecture further constrains bits 12:0 of
hideleg.

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timing(CSR): using addr/wdata after 1 cycle for writing frontend and memory (#4119)

Register 1 cycle addr and wdata, then write to frontend and memory.