xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala (revision 8882eb685de93177da606ee717b5ec8e459a768a) 
1package xiangshan.backend.fu.wrapper
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility._
7import xiangshan._
8import xiangshan.backend.fu.NewCSR._
9import xiangshan.backend.fu.util._
10import xiangshan.backend.fu.{FuConfig, FuncUnit}
11import device._
12import system.HasSoCParameter
13import xiangshan.ExceptionNO._
14import xiangshan.backend.Bundles.TrapInstInfo
15import xiangshan.backend.decode.Imm_Z
16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState
17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode
18import xiangshan.backend.rob.RobPtr
19import xiangshan.frontend.FtqPtr
20import CSRConst._
21
22class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
23  with HasCircularQueuePtrHelper with HasCriticalErrors
24{
25  val csrIn = io.csrio.get
26  val csrOut = io.csrio.get
27  val csrToDecode = io.csrToDecode.get
28
29  val setFsDirty = csrIn.fpu.dirty_fs
30  val setFflags = csrIn.fpu.fflags
31
32  val setVsDirty = csrIn.vpu.dirty_vs
33  val setVstart = csrIn.vpu.set_vstart
34  val setVtype = csrIn.vpu.set_vtype
35  val setVxsat = csrIn.vpu.set_vxsat
36  val vlFromPreg = csrIn.vpu.vl
37
38  val flushPipe = Wire(Bool())
39  val flush = io.flush.valid
40
41  /** Alias of input signals */
42  val (valid, src1, imm, func) = (
43    io.in.valid,
44    io.in.bits.data.src(0),
45    io.in.bits.data.imm(Imm_Z().len - 1, 0),
46    io.in.bits.ctrl.fuOpType
47  )
48
49  // split imm/src1/rd from IMM_Z: src1/rd for tval
50  val addr = Imm_Z().getCSRAddr(imm)
51  val rd   = Imm_Z().getRD(imm)
52  val rs1  = Imm_Z().getRS1(imm)
53  val imm5 = Imm_Z().getImm5(imm)
54  val csri = ZeroExt(imm5, XLEN)
55
56  private val isEcall  = CSROpType.isSystemOp(func) && addr === privEcall
57  private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak
58  private val isMNret  = CSROpType.isSystemOp(func) && addr === privMNret
59  private val isMret   = CSROpType.isSystemOp(func) && addr === privMret
60  private val isSret   = CSROpType.isSystemOp(func) && addr === privSret
61  private val isDret   = CSROpType.isSystemOp(func) && addr === privDret
62  private val isWfi    = CSROpType.isWfi(func)
63  private val isCSRAcc = CSROpType.isCsrAccess(func)
64
65  val csrMod = Module(new NewCSR)
66  val trapInstMod = Module(new TrapInstMod)
67  val trapTvalMod = Module(new TrapTvalMod)
68
69  private val privState = csrMod.io.status.privState
70  // The real reg value in CSR, with no read mask
71  private val regOut = csrMod.io.out.bits.regOut
72  private val src = Mux(CSROpType.needImm(func), csri, src1)
73  private val wdata = LookupTree(func, Seq(
74    CSROpType.wrt  -> src1,
75    CSROpType.set  -> (regOut | src1),
76    CSROpType.clr  -> (regOut & (~src1).asUInt),
77    CSROpType.wrti -> csri,
78    CSROpType.seti -> (regOut | csri),
79    CSROpType.clri -> (regOut & (~csri).asUInt),
80  ))
81
82  private val csrAccess = valid && CSROpType.isCsrAccess(func)
83  private val csrWen = valid && (
84    CSROpType.isCSRRW(func) ||
85    CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U
86  )
87  private val csrRen = valid && (
88    CSROpType.isCSRRW(func) && rd =/= 0.U ||
89    CSROpType.isCSRRSorRC(func)
90  )
91
92  private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire)
93  private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire)
94
95  private val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire)
96  private val thisRobIdx = Wire(new RobPtr)
97  when (io.in.valid) {
98    thisRobIdx := io.in.bits.ctrl.robIdx
99  }.otherwise {
100    thisRobIdx := robIdxReg
101  }
102  private val redirectFlush = thisRobIdx.needFlush(io.flush)
103
104  csrMod.io.in match {
105    case in =>
106      in.valid := valid
107      in.bits.wen := csrWen
108      in.bits.ren := csrRen
109      in.bits.op  := CSROpType.getCSROp(func)
110      in.bits.addr := addr
111      in.bits.src := src
112      in.bits.wdata := wdataReg
113      in.bits.mret := isMret
114      in.bits.mnret := isMNret
115      in.bits.sret := isSret
116      in.bits.dret := isDret
117      in.bits.redirectFlush := redirectFlush
118  }
119  csrMod.io.trapInst := trapInstMod.io.currentTrapInst
120  csrMod.io.fetchMalTval := trapTvalMod.io.tval
121  csrMod.io.fromMem.excpVA  := csrIn.memExceptionVAddr
122  csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr
123  csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE
124
125  csrMod.io.fromRob.trap.valid := csrIn.exception.valid
126  csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc
127  csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr
128  csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr
129  // Todo: shrink the width of trap vector.
130  // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle.
131  csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt
132  csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt
133  csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep
134  csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix
135  csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt
136  csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger
137  csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls
138  csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr
139  csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE
140
141  csrMod.io.fromRob.commit.fflags := setFflags
142  csrMod.io.fromRob.commit.fsDirty := setFsDirty
143  csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid
144  csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits
145  csrMod.io.fromRob.commit.vsDirty := setVsDirty
146  csrMod.io.fromRob.commit.vstart := setVstart
147  csrMod.io.fromRob.commit.vl := vlFromPreg
148  // Todo: correct vtype
149  csrMod.io.fromRob.commit.vtype.valid := setVtype.valid
150  csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1)
151  csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7)
152  csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6)
153  csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3)
154  csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0)
155
156  csrMod.io.fromRob.commit.instNum.valid := true.B  // Todo: valid control signal
157  csrMod.io.fromRob.commit.instNum.bits  := csrIn.perf.retiredInstr
158
159  csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr
160
161  csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy
162
163  csrMod.io.perf  := csrIn.perf
164
165  csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip
166  csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip
167  csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip
168  csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip
169  csrMod.platformIRP.STIP := false.B
170  csrMod.platformIRP.VSEIP := false.B // Todo
171  csrMod.platformIRP.VSTIP := false.B // Todo
172  csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug
173  csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43
174  csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31
175
176  csrMod.io.fromTop.hartId := io.csrin.get.hartId
177  csrMod.io.fromTop.clintTime := io.csrin.get.clintTime
178  csrMod.io.fromTop.l2FlushDone := io.csrin.get.l2FlushDone
179  csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState
180  private val csrModOutValid = csrMod.io.out.valid
181  private val csrModOut      = csrMod.io.out.bits
182
183  trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true)
184  trapInstMod.io.fromRob.flush.valid := io.flush.valid
185  trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx
186  trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset
187  trapInstMod.io.faultCsrUop.valid         := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI)
188  trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire)
189  trapInstMod.io.faultCsrUop.bits.imm      := DataHoldBypass(io.in.bits.data.imm, io.in.fire)
190  trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr    := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire)
191  trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire)
192  // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs.
193  trapInstMod.io.readClear := (csrMod.io.fromRob.trap match {
194    case t =>
195      t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI))
196  })
197
198  trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate
199  trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc
200  trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr
201  trapTvalMod.io.fromCtrlBlock.flush := io.flush
202  trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr
203
204  private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256))
205  imsic.i.hartId := io.csrin.get.hartId
206  imsic.i.msiInfo := io.csrin.get.msiInfo
207  imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid
208  imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr
209  imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt
210  imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt
211  imsic.i.csr.vgein := csrMod.toAIA.vgein
212  imsic.i.csr.mClaim := csrMod.toAIA.mClaim
213  imsic.i.csr.sClaim := csrMod.toAIA.sClaim
214  imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim
215  imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid
216  imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op
217  imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data
218
219  csrMod.fromAIA.rdata.valid        := imsic.o.csr.rdata.valid
220  csrMod.fromAIA.rdata.bits.data    := imsic.o.csr.rdata.bits.rdata
221  csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal
222  csrMod.fromAIA.meip    := imsic.o.meip
223  csrMod.fromAIA.seip    := imsic.o.seip
224  csrMod.fromAIA.vseip   := imsic.o.vseip
225  csrMod.fromAIA.mtopei  := imsic.o.mtopei
226  csrMod.fromAIA.stopei  := imsic.o.stopei
227  csrMod.fromAIA.vstopei := imsic.o.vstopei
228
229  private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo:
230
231  exceptionVec(EX_BP    ) := DataHoldBypass(isEbreak, false.B, io.in.fire)
232  exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire)
233  exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire)
234  exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire)
235  exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire)
236  exceptionVec(EX_II    ) := csrMod.io.out.bits.EX_II
237  exceptionVec(EX_VI    ) := csrMod.io.out.bits.EX_VI
238
239  val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak
240
241  flushPipe := csrMod.io.out.bits.flushPipe
242
243  // tlb
244  val tlb = Wire(new TlbCsrBundle)
245  tlb.satp.changed  := csrMod.io.tlb.satpASIDChanged
246  tlb.satp.mode     := csrMod.io.tlb.satp.MODE.asUInt
247  tlb.satp.asid     := csrMod.io.tlb.satp.ASID.asUInt
248  tlb.satp.ppn      := csrMod.io.tlb.satp.PPN.asUInt
249  tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged
250  tlb.vsatp.mode    := csrMod.io.tlb.vsatp.MODE.asUInt
251  tlb.vsatp.asid    := csrMod.io.tlb.vsatp.ASID.asUInt
252  tlb.vsatp.ppn     := csrMod.io.tlb.vsatp.PPN.asUInt
253  tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged
254  tlb.hgatp.mode    := csrMod.io.tlb.hgatp.MODE.asUInt
255  tlb.hgatp.vmid    := csrMod.io.tlb.hgatp.VMID.asUInt
256  tlb.hgatp.ppn     := csrMod.io.tlb.hgatp.PPN.asUInt
257  tlb.mbmc.BME      := csrMod.io.tlb.mbmc.BME.asUInt
258  tlb.mbmc.CMODE    := csrMod.io.tlb.mbmc.CMODE.asUInt
259  tlb.mbmc.BCLEAR   := csrMod.io.tlb.mbmc.BCLEAR.asUInt
260  tlb.mbmc.BMA      := csrMod.io.tlb.mbmc.BMA.asUInt
261
262  // expose several csr bits for tlb
263  tlb.priv.mxr := csrMod.io.tlb.mxr
264  tlb.priv.sum := csrMod.io.tlb.sum
265  tlb.priv.vmxr := csrMod.io.tlb.vmxr
266  tlb.priv.vsum := csrMod.io.tlb.vsum
267  tlb.priv.spvp := csrMod.io.tlb.spvp
268  tlb.priv.virt := csrMod.io.tlb.dvirt
269  tlb.priv.imode := csrMod.io.tlb.imode
270  tlb.priv.dmode := csrMod.io.tlb.dmode
271
272  // Svpbmt extension enable
273  tlb.mPBMTE := csrMod.io.tlb.mPBMTE
274  tlb.hPBMTE := csrMod.io.tlb.hPBMTE
275
276  // pointer masking extension
277  tlb.pmm := csrMod.io.tlb.pmm
278
279  /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */
280  io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR
281  io.out.valid := csrModOutValid
282  io.out.bits.ctrl.exceptionVec.get := exceptionVec
283  io.out.bits.ctrl.flushPipe.get := flushPipe
284  io.out.bits.res.data := csrMod.io.out.bits.rData
285
286  /** initialize NewCSR's io_out_ready from wrapper's io */
287  csrMod.io.out.ready := io.out.ready
288
289  io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire)
290  val redirect = io.out.bits.res.redirect.get.bits
291  redirect := 0.U.asTypeOf(redirect)
292  redirect.level := RedirectLevel.flushAfter
293  redirect.robIdx := robIdxReg
294  redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire)
295  redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire)
296  redirect.cfiUpdate.predTaken := true.B
297  redirect.cfiUpdate.taken := true.B
298  redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc
299  redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF
300  redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF
301  redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF
302  // Only mispred will send redirect to frontend
303  redirect.cfiUpdate.isMisPred := true.B
304
305  connectNonPipedCtrlSingal
306
307  override val criticalErrors = csrMod.getCriticalErrors
308  generateCriticalErrors()
309
310  // Todo: summerize all difftest skip condition
311  csrOut.isPerfCnt  := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire)
312  csrOut.fpu.frm    := csrMod.io.status.fpState.frm.asUInt
313  csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt
314  csrOut.vpu.vxrm   := csrMod.io.status.vecState.vxrm.asUInt
315
316  csrOut.isXRet := isXRet
317
318  csrOut.trapTarget := csrMod.io.out.bits.targetPc
319  csrOut.interrupt := csrMod.io.status.interrupt
320  csrOut.wfi_event := csrMod.io.status.wfiEvent
321
322  csrOut.tlb := tlb
323
324  csrOut.debugMode := csrMod.io.status.debugMode
325
326  csrOut.traceCSR := csrMod.io.status.traceCSR
327
328  csrOut.customCtrl match {
329    case custom =>
330      custom.pf_ctrl                  := csrMod.io.status.custom.pf_ctrl
331      // Load violation predictor
332      custom.lvpred_disable           := csrMod.io.status.custom.lvpred_disable
333      custom.no_spec_load             := csrMod.io.status.custom.no_spec_load
334      custom.storeset_wait_store      := csrMod.io.status.custom.storeset_wait_store
335      custom.storeset_no_fast_wakeup  := csrMod.io.status.custom.storeset_no_fast_wakeup
336      custom.lvpred_timeout           := csrMod.io.status.custom.lvpred_timeout
337      // Branch predictor
338      custom.bp_ctrl                  := csrMod.io.status.custom.bp_ctrl
339      // Memory Block
340      custom.sbuffer_threshold                := csrMod.io.status.custom.sbuffer_threshold
341      custom.ldld_vio_check_enable            := csrMod.io.status.custom.ldld_vio_check_enable
342      custom.soft_prefetch_enable             := csrMod.io.status.custom.soft_prefetch_enable
343      custom.cache_error_enable               := csrMod.io.status.custom.cache_error_enable
344      custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable
345      custom.hd_misalign_st_enable            := csrMod.io.status.custom.hd_misalign_st_enable
346      custom.hd_misalign_ld_enable            := csrMod.io.status.custom.hd_misalign_ld_enable
347      custom.power_down_enable                := csrMod.io.status.custom.power_down_enable
348      custom.flush_l2_enable                  := csrMod.io.status.custom.flush_l2_enable
349      // Rename
350      custom.fusion_enable            := csrMod.io.status.custom.fusion_enable
351      custom.wfi_enable               := csrMod.io.status.custom.wfi_enable
352      // distribute csr write signal
353      // write to frontend and memory
354      custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal
355      custom.distribute_csr.w.bits.addr := waddrReg
356      custom.distribute_csr.w.bits.data := wdataReg
357      // rename single step
358      custom.singlestep := csrMod.io.status.singleStepFlag
359      // trigger
360      custom.frontend_trigger := csrMod.io.status.frontendTrigger
361      custom.mem_trigger      := csrMod.io.status.memTrigger
362      // virtual mode
363      custom.virtMode := csrMod.io.status.privState.V.asBool
364      // xstatus.fs field is off
365      custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff
366  }
367
368  csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType
369  csrOut.criticalErrorState := csrMod.io.status.criticalErrorState
370
371  csrToDecode := csrMod.io.toDecode
372}
373
374class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{
375  val hartId = Input(UInt(8.W))
376  val msiInfo = Input(ValidIO(new MsiInfoBundle))
377  val criticalErrorState = Input(Bool())
378  val clintTime = Input(ValidIO(UInt(64.W)))
379  val l2FlushDone = Input(Bool())
380  val trapInstInfo = Input(ValidIO(new TrapInstInfo))
381  val fromVecExcpMod = Input(new Bundle {
382    val busy = Bool()
383  })
384}
385
386class CSRToDecode(implicit p: Parameters) extends XSBundle {
387  val illegalInst = new Bundle {
388    /**
389     * illegal sfence.vma, sinval.vma
390     * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU
391     */
392    val sfenceVMA = Bool()
393
394    /**
395     * illegal sfence.w.inval sfence.inval.ir
396     * raise EX_II when isModeHU
397     */
398    val sfencePart = Bool()
399
400    /**
401     * illegal hfence.gvma, hinval.gvma
402     * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU
403     * the condition is the same as sfenceVMA
404     */
405    val hfenceGVMA = Bool()
406
407    /**
408     * illegal hfence.vvma, hinval.vvma
409     * raise EX_II when isModeHU
410     */
411    val hfenceVVMA = Bool()
412
413    /**
414     * illegal hlv, hlvx, and hsv
415     * raise EX_II when isModeHU && hstatus.HU=0
416     */
417    val hlsv = Bool()
418
419    /**
420     * decode all fp inst or all vecfp inst
421     * raise EX_II when FS=Off
422     */
423    val fsIsOff = Bool()
424
425    /**
426     * decode all vec inst
427     * raise EX_II when VS=Off
428     */
429    val vsIsOff = Bool()
430
431    /**
432     * illegal wfi
433     * raise EX_II when isModeHU || !isModeM && mstatus.TW=1
434     */
435    val wfi = Bool()
436
437    /**
438     * illegal wrs_nto
439     * raise EX_II when !isModeM && mstatus.TW=1
440     */
441    val wrs_nto = Bool()
442
443    /**
444     * frm reserved
445     * raise EX_II when frm.data > 4
446     */
447    val frm = Bool()
448
449    /**
450     * illegal CBO.ZERO
451     * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE
452     */
453    val cboZ = Bool()
454
455    /**
456     * illegal CBO.CLEAN/FLUSH
457     * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE
458     */
459    val cboCF = Bool()
460
461    /**
462     * illegal CBO.INVAL
463     * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off
464     */
465    val cboI = Bool()
466  }
467
468  val virtualInst = new Bundle {
469    /**
470     * illegal sfence.vma, svinval.vma
471     * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU
472     */
473    val sfenceVMA = Bool()
474
475    /**
476     * illegal sfence.w.inval sfence.inval.ir
477     * raise EX_VI when isModeVU
478     */
479    val sfencePart = Bool()
480
481    /**
482     * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma
483     * raise EX_VI when isModeVS || isModeVU
484     */
485    val hfence = Bool()
486
487    /**
488     * illegal hlv, hlvx, and hsv
489     * raise EX_VI when isModeVS || isModeVU
490     */
491    val hlsv = Bool()
492
493    /**
494     * illegal wfi
495     * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1
496     */
497    val wfi = Bool()
498
499    /**
500     * illegal wrs_nto
501     * raise EX_VI when privState.V && mstatus.TW=0 && hstatus.VTW=1
502     */
503    val wrs_nto = Bool()
504
505    /**
506     * illegal CBO.ZERO
507     * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE))
508     */
509    val cboZ = Bool()
510
511    /**
512     * illegal CBO.CLEAN/FLUSH
513     * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE))
514     */
515    val cboCF = Bool()
516
517    /**
518     * illegal CBO.INVAL <br/>
519     * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/>
520     *   isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/>
521     *   isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/>
522     * ) <br/>
523     */
524    val cboI = Bool()
525  }
526
527  val special = new Bundle {
528    /**
529     * execute CBO.INVAL and perform flush operation when <br/>
530     * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/>
531     * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/>
532     * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/>
533     * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/>
534     */
535    val cboI2F = Bool()
536  }
537}