build(version): inject git commit SHA to hardware CommitIDModule (#3818)

fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn

* Count overflow only from hardware incrementes of counter registers
* Through XiangShan->difftest->NEMU, to make NEMU get mhpmeve

fix(csr): add difftest of mhpmevent overflow to diff csr mhpmeventn

* Count overflow only from hardware incrementes of counter registers
* Through XiangShan->difftest->NEMU, to make NEMU get mhpmevent.of

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fix(mhpmevent): add MhpmeventBundle for mhpmevent csr.

fix(CSR): remove reg in `scountovf`.

fix(CSR): debug Interrupt is not invisible to M-mode (#3826)

feat(dbltrp) : add support for critical error (#3793)

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defco

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)

* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig

Including:
* fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
* fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
* feat(trigger): add trigger support for rva.
* configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

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* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.

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fix(csr): fix intermediate storage reg for EX_II and EX_VI (#3771)

Use one reg to store EX_II/EX_VI when output not fired.

fix(Ebreak): use isPcBkpt to hold exception raised by ebreak (#3769)

* This signal is only used to distinguish EX_BP store pc or load/store
address in {m|s|vs}tval.

fix(Breakpoint): memory trigger set {m|s|vs}tval with faulting address (#3762)

* This commit fix the value of {m|s|vs}tval when load/store/atomic
trigger fire. The faulting address should be writte

fix(Breakpoint): memory trigger set {m|s|vs}tval with faulting address (#3762)

* This commit fix the value of {m|s|vs}tval when load/store/atomic
trigger fire. The faulting address should be written to tval.

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fix(wfi): WFI should be treated as `nop` when stepped or in dmode (#3715)

fix(csr): Delay trap of hvictl inject passed to difftest until VecExcpMod not busy (#3744)

fix(csr): fix asynchronous access IMSIC (#3725)

* Add asynchronous write IMSIC
* Modify the condition for `io.out.valid` to be pulled high when
accessing IMSIC asynchronously

fix(csr): fix read/write stimecmp raise EX_II

* Access stimecmp/vstimecmp raise EX_II when mcounteren.TM = 0 or menvcfg.STCE = 0 in less M mode

fix(csr): fix local counter overflow interrupt req to diff mip.lcofip (#3710)

fix(CSR): `targetPcUpdate` do not need `io.in.fire` (#3707)

feat(HPM): enable HPMs in CoupledL2 and print them (#3708)

* Bump CoupledL2 and connect perf events.
* Update the number of HPMs
* Detail names of HPM can be printed now. The previous implementati

feat(HPM): enable HPMs in CoupledL2 and print them (#3708)

* Bump CoupledL2 and connect perf events.
* Update the number of HPMs
* Detail names of HPM can be printed now. The previous implementation
has been removed in
[#3631](https://github.com/OpenXiangShan/XiangShan/pull/3631).

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fix(CSR): fix shadow write to PMA and customize CSRs (#3703)

* Use wenLegal in NewCSR as distribute csr write wen signal

fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

fix(CSR): fix shadow write for many CSRs (#3701)

* Although EX_II will be raised when access these CSRs in some illegal
ways(e.g. writing pmpcfg in S mode), the regs in these CSRs will always
be c

fix(CSR): fix shadow write for many CSRs (#3701)

* Although EX_II will be raised when access these CSRs in some illegal
ways(e.g. writing pmpcfg in S mode), the regs in these CSRs will always
be changed by wdata. The reason for the mistake is that the wen of these
CSRs is assigned directly to wen of NewCSR instead of wenLegal which
only assert when writing CSR in some legal ways.
* Fixed CSRs are pmpcfgs, pmpaddrs, miregs, siregs and vsiregs.
* Todo: all wen and wdata of CSRModule assigned in the same for loop

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fix(CSR): assert vsatpASIDChanged when actually write vsatp by satp (#3700)

* Use CSR.w.wen insread of addr comparation to avoid this mistake.

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege

fix(Trigger): remove tcontrol in trigger module.

* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.

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feat(Trigger): Trigger Module support mcontrol6.

fix(fof): always use tail undisturbed when vl updated by un-raised exception.

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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