History log of /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala (Results 1 – 9 of 9)
Revision Date Author Comments
# a2fa0ad9 02-Dec-2024 xiaofeibao <[email protected]>

area(backend): only use startAddr in pcMem


# e6f36bc4 09-Sep-2024 xiaofeibao <[email protected]>

timing(BranchUnit): fix timing of target


# c1b28b66 09-Sep-2024 Tang Haojin <[email protected]>

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

show more ...


# 54c6d89d 24-Jul-2024 xiaofeibao-xjtu <[email protected]>

Redirect fix timing (#3209)


# c1e19666 04-Jan-2024 xiaofeibao-xjtu <[email protected]>

backend: implement uncertain latency exeUnit WbArbiter


# 83ba63b3 11-Oct-2023 Xuan Hu <[email protected]>

fix merge error


# 78115a00 22-May-2023 Xuan Hu <[email protected]>

fu: add PipedFuncUnit and refactor piped function units

* all piped function units should extends PipedFuncUnit


# 6a35d972 09-May-2023 Xuan Hu <[email protected]>

fu: split io bundle into ctrl and data parts


# 730cfbc0 16-Apr-2023 Xuan Hu <[email protected]>

backend: merge v2backend into backend