1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utility.SignExt 6import xiangshan.backend.decode.ImmUnion 7import xiangshan.backend.fu.{BranchModule, FuConfig, FuncUnit} 8import xiangshan.backend.datapath.DataConfig.VAddrData 9import xiangshan.{RedirectLevel, XSModule} 10 11class AddrAddModule(len: Int)(implicit p: Parameters) extends XSModule { 12 val io = IO(new Bundle { 13 val pc = Input(UInt(len.W)) 14 val taken = Input(Bool()) 15 val isRVC = Input(Bool()) 16 val offset = Input(UInt(12.W)) // branch inst only support 12 bits immediate num 17 val target = Output(UInt(len.W)) 18 }) 19 io.target := io.pc + Mux(io.taken, 20 SignExt(ImmUnion.B.toImm32(io.offset), len), 21 Mux(io.isRVC, 2.U, 4.U) 22 ) 23} 24 25class BranchUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 26 val dataModule = Module(new BranchModule) 27 val addModule = Module(new AddrAddModule(VAddrData().dataWidth)) 28 dataModule.io.src(0) := io.in.bits.data.src(0) // rs1 29 dataModule.io.src(1) := io.in.bits.data.src(1) // rs2 30 dataModule.io.func := io.in.bits.ctrl.fuOpType 31 dataModule.io.pred_taken := io.in.bits.ctrl.predictInfo.get.taken 32 33 addModule.io.pc := io.in.bits.data.pc.get // pc 34 addModule.io.offset := io.in.bits.data.imm // imm 35 addModule.io.taken := dataModule.io.taken 36 addModule.io.isRVC := io.in.bits.ctrl.preDecode.get.isRVC 37 38 io.out.valid := io.in.valid 39 io.in.ready := io.out.ready 40 41 io.out.bits.res.data := 0.U 42 io.out.bits.res.redirect.get match { 43 case redirect => 44 redirect.valid := io.out.valid && dataModule.io.mispredict 45 redirect.bits := 0.U.asTypeOf(io.out.bits.res.redirect.get.bits) 46 redirect.bits.level := RedirectLevel.flushAfter 47 redirect.bits.robIdx := io.in.bits.ctrl.robIdx 48 redirect.bits.ftqIdx := io.in.bits.ctrl.ftqIdx.get 49 redirect.bits.ftqOffset := io.in.bits.ctrl.ftqOffset.get 50 redirect.bits.cfiUpdate.isMisPred := dataModule.io.mispredict 51 redirect.bits.cfiUpdate.taken := dataModule.io.taken 52 redirect.bits.cfiUpdate.predTaken := dataModule.io.pred_taken 53 redirect.bits.cfiUpdate.target := addModule.io.target 54 redirect.bits.cfiUpdate.pc := io.in.bits.data.pc.get 55 } 56 connect0LatencyCtrlSingal 57} 58