fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is upda

fix(CSR): fix xTIP update in sstcIRGen (#4157)

* The STIP signal is updated when:
* time.valid of clint
* stimecmp CSR is written
* menvcfg CSR is written

* The VSTIP signal is updated when:
* time.valid of clint
* vstimecmp CSR is written
* htimedelta CSR is written
* menvcfg CSR is written
* henvcfg CSR is written

Co-authored-by: Xuan Hu <[email protected]>

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NewCSR: update time CSR

* Read time CSR in VS or VU mode return htimedelta + actual value of time
* Add stime, vstime output IO to saving adder

NewCSR: support Sstc extension

* Add `stimecmp` and `vstimecmp` CSR.
* Add `STIP` and `VSTIP` interrupt.
* Add `STCE` field in `menvcfg` and `henvcfg` to enable Sstc extension.