1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5 6class SstcInterruptGen extends Module { 7 val i = IO(Input(new Bundle { 8 val time = ValidIO(UInt(64.W)) 9 val htimedelta = UInt(64.W) 10 val stimecmp = UInt(64.W) 11 val vstimecmp = UInt(64.W) 12 val menvcfgSTCE = Bool() 13 val henvcfgSTCE = Bool() 14 })) 15 val o = IO(Output(new Bundle { 16 val STIP = Bool() 17 val VSTIP = Bool() 18 })) 19 20 // Guard TIP by envcfg.STCE to avoid wrong assertion of time interrupt 21 o.STIP := RegEnable(i.time.bits >= i.stimecmp, false.B, i.time.valid && i.menvcfgSTCE) 22 o.VSTIP := RegEnable(i.time.bits + i.htimedelta >= i.vstimecmp, false.B, i.time.valid && i.henvcfgSTCE) 23} 24