| #
39ec22f6 |
| 13-Feb-2025 |
Guanghui Cheng <[email protected]> |
fix(Mcontrol6): fix writing mcontrol6.dmode for trigger chain (#4256)
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| #
a751b11a |
| 11-Nov-2024 |
chengguanghui <[email protected]> |
fix(dcsr): debug support critical error state
* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.
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| #
1e49aeed |
| 25-Oct-2024 |
chengguanghui <[email protected]> |
fix(CSR): fix dcsr to support stopcount & stoptime
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| #
c08f49a0 |
| 30-Sep-2024 |
chengguanghui <[email protected]> |
fix(Trigger): remove tcontrol in trigger module.
* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege
fix(Trigger): remove tcontrol in trigger module.
* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.
show more ...
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| #
cc6e4cb5 |
| 29-Sep-2024 |
chengguanghui <[email protected]> |
feat(Trigger): Trigger Module support mcontrol6.
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| #
7e0f64b0 |
| 21-Aug-2024 |
Guanghui Cheng <[email protected]> |
Trigger: refactor trigger information in pipeline. (#3403)
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| #
afc7cd8c |
| 07-Aug-2024 |
Xuan Hu <[email protected]> |
CSR: use "ignore illegal write" WARL strategy for tselect (#3353)
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| #
3e8a0170 |
| 25-Jul-2024 |
Xuan Hu <[email protected]> |
ROB: clear flushPipe when the enq uop has exception (#3281)
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| #
e3da8bad |
| 22-Jul-2024 |
Tang Haojin <[email protected]> |
build: purge chisel 3 and add deprecation check (#3250)
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| #
499d09b3 |
| 16-Jul-2024 |
sinceforYy <[email protected]> |
NewCSR: set legal init value to WARL Field
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| #
0f9a14c6 |
| 14-Jun-2024 |
chengguanghui <[email protected]> |
NewCSR: fixed dpc
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| #
21c4da12 |
| 06-Jun-2024 |
chengguanghui <[email protected]> |
NewCSR: parameterized tselect's width
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| #
b51a1abd |
| 04-Jun-2024 |
chengguanghui <[email protected]> |
NewCSR: connected perfevent to newcsr
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| #
657432e4 |
| 29-May-2024 |
chengguanghui <[email protected]> |
NewCSR: Add Trigger CSR tcontrol
* add csr tcontrol.
* medeleg(EX_BP) hard-wired to 0. Parter 5.4 in debug spec. tcontrol is implemented. medeleg(3) is hard-wired to 0.
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| #
a7a6d0a6 |
| 23-May-2024 |
chengguanghui <[email protected]> |
NewCSR: Refactor CSR about Debug
* add CSR: trigger csr & debug csr
* add CSR event: TrapEntryDEvent & DretEvent
* fixed trigger's comparison func between Consecutive pc and tdada2
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| #
8aa89407 |
| 20-May-2024 |
Xuan Hu <[email protected]> |
NewCSR: change the type of rdata to UInt in CSRModule
* Since the rdata bundle is used to get CSR read value, we change the type of rdata to UInt(64.W) and do all needed expansions before the value
NewCSR: change the type of rdata to UInt in CSRModule
* Since the rdata bundle is used to get CSR read value, we change the type of rdata to UInt(64.W) and do all needed expansions before the value assigned to rdata bundles.
show more ...
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| #
1a610887 |
| 25-Apr-2024 |
sinceforYy <[email protected]> |
NewCSR: fix Debug and Custom CSR
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| #
1d72599b |
| 22-Apr-2024 |
sinceforYy <[email protected]> |
NewCSR: add trigger CSR
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| #
223cba9d |
| 22-Apr-2024 |
Xuan Hu <[email protected]> |
NewCSR: add debug csr in csrMods and csrMaps
|