xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala (revision 8aa8940798b2a7869c6dca150735fd2372811310) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import CSRConfig._
6import xiangshan.backend.fu.NewCSR.CSRDefines._
7import xiangshan.backend.fu.NewCSR.CSRDefines.{
8  CSRWARLField => WARL,
9  CSRRWField => RW,
10  CSRROField => RO,
11}
12import xiangshan.backend.fu.NewCSR.CSRFunc._
13
14import scala.collection.immutable.SeqMap
15
16trait DebugLevel { self: NewCSR =>
17  val tselect = Module(new CSRModule("Tselect"))
18    .setAddr(0x7A0)
19
20//  val tdata1 = Module(new CSRModule("tdata1", new Tdata1Bundle) {
21//    reg.TYPE := Mux(wdata.TYPE.isLegal, wdata.TYPE.asUInt, Tdata1Type.Disabled.asUInt).asTypeOf(reg.TYPE)
22//    reg.DMODE := (wdata.DMODE.asBool && debugMode).asTypeOf(reg.DMODE)
23//    reg.DATA := Mux(wdata.TYPE.asUInt === Tdata1Type.Mcontrol.asUInt, 0.U, 0.U).asTypeOf(reg.DATA)
24//  })
25  val tdata1 = Module(new CSRModule("Tdata1")) // Todo
26    .setAddr(0x7A1)
27
28  val dcsr = Module(new CSRModule("Dcsr", new DcsrBundle))
29    .setAddr(0x7B0)
30
31  val dpc = Module(new CSRModule("Dpc", new Dpc))
32    .setAddr(0x7B1)
33
34  val dscratch0 = Module(new CSRModule("Dscratch0"))
35    .setAddr(0x7B2)
36
37  val dscratch1 = Module(new CSRModule("Dscratch1"))
38    .setAddr(0x7B3)
39
40  val debugCSRMods = Seq(
41    tselect,
42    tdata1,
43    dcsr,
44    dpc,
45    dscratch0,
46    dscratch1,
47  )
48
49  val debugCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], UInt)] = SeqMap.from(
50    debugCSRMods.map(csr => csr.addr -> (csr.w -> csr.rdata)).iterator
51  )
52
53  val debugCSROutMap: SeqMap[Int, UInt] = SeqMap.from(
54    debugCSRMods.map(csr => csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt).iterator
55  )
56}
57
58class Tdata1Bundle extends CSRBundle {
59  val TYPE  = Tdata1Type(63, 60, wNoFilter).withReset(Tdata1Type.Disabled)
60  val DMODE = WARL(59, wNoFilter).withReset(0.U)
61  val DATA  = WARL(58, 0, wNoFilter) // Todo:
62}
63
64class DcsrBundle extends CSRBundle {
65  val DEBUGVER  = DcsrDebugVer(31, 28).withReset(DcsrDebugVer.Spec) // Debug implementation as it described in 0.13 draft // todo
66  // All ebreak Privileges are RW, instead of WARL, since XiangShan support U/S/VU/VS.
67  val EBREAKVS  =           RW(    17).withReset(0.U)
68  val EBREAKVU  =           RW(    16).withReset(0.U)
69  val EBREAKM   =           RW(    15).withReset(0.U)
70  val EBREAKS   =           RW(    13).withReset(0.U)
71  val EBREAKU   =           RW(    12).withReset(0.U)
72  // STEPIE is RW, instead of WARL, since XiangShan support interrupts being enabled single stepping.
73  val STEPIE    =           RW(    11).withReset(0.U)
74  val STOPCOUNT =           RO(    10).withReset(0.U) // Stop count updating has not been supported
75  val STOPTIME  =           RO(     9).withReset(0.U) // Stop time updating has not been supported
76  val CAUSE     =    DcsrCause( 8,  6).withReset(DcsrCause.none)
77  val V         =     VirtMode(     5).withReset(VirtMode.Off)
78  // MPRVEN is RW, instead of WARL, since XiangShan support use mstatus.mprv in debug mode
79  // Whether use mstatus.mprv
80  val MPRVEN    =           RW(     4).withReset(0.U)
81  // TODO: support non-maskable interrupt
82  val NMIP      =           RO(     3).withReset(0.U)
83  // MPRVEN is RW, instead of WARL, since XiangShan support use mstatus.mprv in debug mode
84  val STEP      =           RW(     2).withReset(0.U)
85  val PRV       =     PrivMode( 1,  0).withReset(PrivMode.M)
86}
87
88class Dpc extends CSRBundle {
89  val ALL = RW(63, 1)
90}
91
92object Tdata1Type extends CSREnum with WARLApply {
93  val None         = Value(0.U)
94  val Legacy       = Value(1.U)
95  val Mcontrol     = Value(2.U)
96  val Icount       = Value(3.U)
97  val Itrigger     = Value(4.U)
98  val Etrigger     = Value(5.U)
99  val Mcontrol6    = Value(6.U)
100  val Tmexttrigger = Value(7.U)
101  val Disabled     = Value(15.U)
102
103  /**
104   * XS supports part of trigger type of Sdtrig extension
105   * @param enum trigger type checked
106   * @return true.B, If XS support this trigger type
107   */
108
109  override def isLegal(enum: CSREnumType): Bool = enum.asUInt === Mcontrol.asUInt
110}
111
112
113object DcsrDebugVer extends CSREnum with ROApply {
114  val None = Value(0.U)
115  val Spec = Value(4.U)
116  val Custom = Value(15.U)
117}
118
119object DcsrCause extends CSREnum with ROApply {
120  val none         = Value(0.U)
121  val ebreak       = Value(1.U)
122  val trigger      = Value(2.U)
123  val haltreq      = Value(3.U)
124  val step         = Value(4.U)
125  val resethaltreq = Value(5.U)
126  val group        = Value(6.U)
127}
128