fix(zvfh): fix zvfh corner case which should support vsew8
* vfwcvtfx,vfwcvtfxu,vfncvtxuf,vfncvtxf,vfncvtrodxuf,vfncvtrodxf should support vsew8

feat(zvfh,zfh): add F16 support

fix(vecException): fix float exception generate when sew <= 16 (#3535)

feat(VceExceptionGen): support Zvfhmin extension (#3493)

Cancel the exception of the Zvfhmin extension instruction and support Zvfhmin extension.

* The Zvfhmin extension refers to the case where

feat(VceExceptionGen): support Zvfhmin extension (#3493)

Cancel the exception of the Zvfhmin extension instruction and support Zvfhmin extension.

* The Zvfhmin extension refers to the case where sew==1, where the
exceptions for VFWCVT_F_F_V and VFNCVT_F_F_W instructions are removed.

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rv64v: exception check for vector widening reduction instructions (#3243)

rv64v: fix fp type generate in exceptionGen and add check for vwsll (#3233)

rv64v: raise illegal exception when instruction is in ZVFH extension (#3221)

rv64v: raise illegal exception when running vector fp16 instructions

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions exce

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions except above instructions, raise
illegal instruction exception
* when modify vstart, blockback and flushpipe

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rv64v: fix exception check for vmvnr instructions (#3111)

rv64v: fix some bugs in vector exception check

decode: fix riscv vector exception checker

* The v0 overlap checking should be done in vector arith/mem insts

decode: add dontTouch in VecExceptionGen to make better verilog

fix merge error

backend: refactor FuType

* use OHEnumeration to represent FuType

vector: move isVector & isVfp to FuType

vector: add VecExceptionGen in decode unit