1package xiangshan.backend.decode 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.rocket.Instructions._ 7import freechips.rocketchip.util.uintToBitPat 8import utility._ 9import utils._ 10import xiangshan._ 11import xiangshan.backend.Bundles.{DecodedInst, DynInst, StaticInst} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Bundles._ 14import xiangshan.backend.decode.isa.bitfield.{InstVType, XSInstBitFields} 15 16object RegNumNotAlign { 17 def apply(reg: UInt, emul: UInt): Bool = { 18 emul === "b101".U && reg(0) =/= 0.U || emul === "b110".U && reg(1, 0) =/= 0.U || emul === "b111".U && reg(2, 0) =/= 0.U 19 } 20} 21 22object NFtoLmul { 23 def apply(nf: UInt): UInt = { 24 LookupTree(nf, List( 25 "b000".U -> 4.U, 26 "b001".U -> 5.U, 27 "b011".U -> 6.U, 28 "b111".U -> 7.U 29 )) 30 } 31} 32 33object LmultoRegNum { 34 def apply(lmul: UInt): UInt = { 35 val numPow = Mux(lmul(2).asBool, lmul(1, 0), 0.U(2.W)) 36 val regNum = 1.U << numPow 37 regNum 38 } 39} 40 41class VecExceptionGen(implicit p: Parameters) extends XSModule{ 42 val io = IO(new Bundle(){ 43 val inst = Input(UInt(32.W)) 44 val decodedInst = Input(new DecodedInst) 45 val vtype = Input(new VType) 46 47 val illegalInst = Output(Bool()) 48 }) 49 50 private val inst: XSInstBitFields = io.inst.asTypeOf(new XSInstBitFields) 51 private val isVector = FuType.isVector(io.decodedInst.fuType) 52 53 private val SEW = io.vtype.vsew(1, 0) 54 private val LMUL = Cat(~io.vtype.vlmul(2), io.vtype.vlmul(1, 0)) 55 56 private val lsStrideInst = Seq( 57 VLE8_V, VLE16_V, VLE32_V, VLE64_V, VSE8_V, VSE16_V, VSE32_V, VSE64_V, 58 VLSE8_V, VLSE16_V, VLSE32_V, VLSE64_V, VSSE8_V, VSSE16_V, VSSE32_V, VSSE64_V, 59 VLE8FF_V, VLE16FF_V, VLE32FF_V, VLE64FF_V 60 ).map(_ === inst.ALL).reduce(_ || _) 61 62 private val lsMaskInst = Seq( 63 VLM_V, VSM_V 64 ).map(_ === inst.ALL).reduce(_ || _) 65 66 private val lsIndexInst = Seq( 67 VLUXEI8_V, VLUXEI16_V, VLUXEI32_V, VLUXEI64_V, VLOXEI8_V, VLOXEI16_V, VLOXEI32_V, VLOXEI64_V, 68 VSUXEI8_V, VSUXEI16_V, VSUXEI32_V, VSUXEI64_V, VSOXEI8_V, VSOXEI16_V, VSOXEI32_V, VSOXEI64_V 69 ).map(_ === inst.ALL).reduce(_ || _) 70 71 private val lsWholeInst = Seq( 72 VL1RE8_V, VL1RE16_V, VL1RE32_V, VL1RE64_V, 73 VL2RE8_V, VL2RE16_V, VL2RE32_V, VL2RE64_V, 74 VL4RE8_V, VL4RE16_V, VL4RE32_V, VL4RE64_V, 75 VL8RE8_V, VL8RE16_V, VL8RE32_V, VL8RE64_V, 76 VS1R_V, VS2R_V, VS4R_V, VS8R_V 77 ).map(_ === inst.ALL).reduce(_ || _) 78 79 private val vdWideningInst = Seq( 80 //int 81 VWADD_VV, VWADD_VX, VWADD_WV, VWADD_WX, VWADDU_VV, VWADDU_VX, VWADDU_WV, VWADDU_WX, 82 VWMACC_VV, VWMACC_VX, VWMACCSU_VV, VWMACCSU_VX, VWMACCU_VV, VWMACCU_VX, VWMACCUS_VX, 83 VWMUL_VV, VWMUL_VX, VWMULSU_VV, VWMULSU_VX, VWMULU_VV, VWMULU_VX, 84 VWSUB_VV, VWSUB_VX, VWSUB_WV, VWSUB_WX, VWSUBU_VV, VWSUBU_VX, VWSUBU_WV, VWSUBU_WX, 85 //fp 86 VFWADD_VF, VFWADD_VV, VFWADD_WF, VFWADD_WV, VFWSUB_VF, VFWSUB_VV, VFWSUB_WF, VFWSUB_WV, 87 VFWMUL_VF, VFWMUL_VV, 88 VFWMACC_VF, VFWMACC_VV, VFWMSAC_VF, VFWMSAC_VV, VFWNMACC_VF, VFWNMACC_VV, VFWNMSAC_VF, VFWNMSAC_VV, 89 VFWCVT_F_F_V, VFWCVT_F_X_V, VFWCVT_F_XU_V, VFWCVT_RTZ_X_F_V, VFWCVT_RTZ_XU_F_V, VFWCVT_X_F_V, VFWCVT_XU_F_V 90 ).map(_ === inst.ALL).reduce(_ || _) 91 92 private val vs2WideningInst = Seq( 93 //int 94 VWADD_WV, VWADD_WX, VWADDU_WV, VWADDU_WX, 95 VWSUB_WV, VWSUB_WX, VWSUBU_WV, VWSUBU_WX, 96 //fp 97 VFWADD_WF, VFWADD_WV, VFWSUB_WF, VFWSUB_WV 98 ).map(_ === inst.ALL).reduce(_ || _) 99 100 private val narrowingInst = Seq( 101 //int 102 VNCLIP_WI, VNCLIP_WV, VNCLIP_WX, VNCLIPU_WI, VNCLIPU_WV, VNCLIPU_WX, 103 VNSRA_WI, VNSRA_WV, VNSRA_WX, VNSRL_WI, VNSRL_WV, VNSRL_WX, 104 //fp 105 VFNCVT_F_F_W, VFNCVT_F_X_W, VFNCVT_F_XU_W, VFNCVT_ROD_F_F_W, VFNCVT_RTZ_X_F_W, VFNCVT_RTZ_XU_F_W, VFNCVT_X_F_W, VFNCVT_XU_F_W 106 ).map(_ === inst.ALL).reduce(_ || _) 107 108 private val intExtInst = Seq( 109 VSEXT_VF2, VSEXT_VF4, VSEXT_VF8, VZEXT_VF2, VZEXT_VF4, VZEXT_VF8 110 ).map(_ === inst.ALL).reduce(_ || _) 111 112 private val acsbInst = Seq( 113 VMADC_VI, VMADC_VIM, VMADC_VV, VMADC_VVM, VMADC_VX, VMADC_VXM, 114 VMSBC_VV, VMSBC_VVM, VMSBC_VX, VMSBC_VXM 115 ).map(_ === inst.ALL).reduce(_ || _) 116 117 private val cmpInst = Seq( 118 //int 119 VMSEQ_VI, VMSEQ_VV, VMSEQ_VX, 120 VMSGT_VI, VMSGT_VX, VMSGTU_VI, VMSGTU_VX, 121 VMSLE_VI, VMSLE_VV, VMSLE_VX, VMSLEU_VI, VMSLEU_VV, VMSLEU_VX, 122 VMSLT_VV, VMSLT_VX, VMSLTU_VV, VMSLTU_VX, 123 VMSNE_VI, VMSNE_VV, VMSNE_VX, 124 //fp 125 VMFEQ_VF, VMFEQ_VV, VMFNE_VF, VMFNE_VV, 126 VMFGE_VF, VMFGT_VF, VMFLE_VF, VMFLE_VV, VMFLT_VF, VMFLT_VV 127 ).map(_ === inst.ALL).reduce(_ || _) 128 129 private val redInst = Seq( 130 VREDAND_VS, VREDMAX_VS, VREDMAXU_VS, VREDMIN_VS, VREDMINU_VS, VREDOR_VS, VREDSUM_VS, VREDXOR_VS, 131 VFREDMAX_VS, VFREDMIN_VS, VFREDOSUM_VS, VFREDUSUM_VS 132 ).map(_ === inst.ALL).reduce(_ || _) 133 134 private val redWideningInst = Seq( 135 VWREDSUM_VS, VWREDSUMU_VS, 136 VFWREDOSUM_VS, VFWREDUSUM_VS 137 ).map(_ === inst.ALL).reduce(_ || _) 138 139 private val maskLogicalInst = Seq( 140 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM 141 ).map(_ === inst.ALL).reduce(_ || _) 142 143 private val maskArithmeticInst = Seq( 144 VCPOP_M, VFIRST_M, VMSBF_M, VMSIF_M, VMSOF_M 145 ).map(_ === inst.ALL).reduce(_ || _) || maskLogicalInst 146 147 private val maskIndexInst = Seq( 148 VIOTA_M, VID_V 149 ).map(_ === inst.ALL).reduce(_ || _) 150 151 private val vmvSingleInst = Seq( 152 VMV_X_S, VMV_S_X, VFMV_F_S, VFMV_S_F 153 ).map(_ === inst.ALL).reduce(_ || _) 154 155 private val vmvWholeInst = Seq( 156 VMV1R_V, VMV2R_V, VMV4R_V, VMV8R_V 157 ).map(_ === inst.ALL).reduce(_ || _) 158 159 private val vrgather16 = VRGATHEREI16_VV === inst.ALL 160 private val vcompress = VCOMPRESS_VM === inst.ALL 161 private val intExt2 = Seq(VSEXT_VF2, VZEXT_VF2).map(_ === inst.ALL).reduce(_ || _) 162 private val intExt4 = Seq(VSEXT_VF4, VZEXT_VF4).map(_ === inst.ALL).reduce(_ || _) 163 private val intExt8 = Seq(VSEXT_VF8, VZEXT_VF8).map(_ === inst.ALL).reduce(_ || _) 164 165 private val notDependVtypeInst = Seq(VSETVLI, VSETIVLI, VSETVL).map(_ === inst.ALL).reduce(_ || _) || lsWholeInst || vmvWholeInst 166 167 168 // 1. inst Illegal 169 private val instIllegal = maskLogicalInst && inst.VM === 0.U 170 171 // 2. vill Illegal 172 private val villIllegal = io.vtype.illegal && isVector && !notDependVtypeInst 173 174 // 3. EEW Illegal 175 private val doubleFpInst = Seq( 176 VFWCVT_F_X_V, VFWCVT_F_XU_V, VFNCVT_RTZ_X_F_W, VFNCVT_RTZ_XU_F_W, VFNCVT_X_F_W, VFNCVT_XU_F_W 177 ).map(_ === inst.ALL).reduce(_ || _) 178 private val fpEewIllegal = FuType.isVfp(io.decodedInst.fuType) && !doubleFpInst && SEW === 0.U 179 180 private val intExtEewIllegal = intExt2 && SEW === 0.U || 181 intExt4 && SEW <= 1.U || 182 intExt8 && SEW <= 2.U 183 184 private val wnEewIllegal = (vdWideningInst || narrowingInst || redWideningInst) && SEW === 3.U 185 186 private val eewIllegal = fpEewIllegal || intExtEewIllegal || wnEewIllegal 187 188 // 4. EMUL Illegal 189 private val lsEmulIllegal = (lsStrideInst || lsIndexInst) && (LMUL +& inst.WIDTH(1, 0) < SEW +& 1.U || LMUL +& inst.WIDTH(1, 0) > SEW +& 7.U) 190 191 private val intExtEmulIllegal = intExt2 && LMUL === 1.U || 192 intExt4 && LMUL <= 2.U || 193 intExt8 && LMUL <= 3.U 194 195 private val wnEmulIllegal = (vdWideningInst || narrowingInst || redWideningInst) && LMUL === 7.U 196 197 private val gather16EmulIllegal = vrgather16 && (LMUL < SEW || LMUL > SEW +& 6.U) 198 199 private val NFIELDS = inst.NF +& 1.U 200 private val segEmul = Mux(lsIndexInst, LMUL, LMUL +& inst.WIDTH(1, 0) - SEW) 201 private val emulNumPow = Mux(segEmul(2), segEmul(1, 0), 0.U(2.W)) 202 private val segRegNum = NFIELDS << emulNumPow 203 private val segRegMax = inst.VD +& segRegNum 204 205 private val lsSegIllegal = (lsStrideInst || lsIndexInst) && inst.NF =/= 0.U && (segRegNum > 8.U || segRegMax > 32.U) 206 207 private val emulIllegal = lsEmulIllegal || intExtEmulIllegal || wnEmulIllegal || gather16EmulIllegal || lsSegIllegal 208 209 // 5. Reg Number Align 210 private val vs1IsMask = maskArithmeticInst || vcompress 211 private val vs1IsSingleElem = redInst 212 private val vs1Eew = Mux(vrgather16, "b01".U, SEW) 213 private val vs1Emul = Mux(vs1IsMask || vs1IsSingleElem, "b100".U, Mux(vrgather16, LMUL +& 1.U - SEW, LMUL)) 214 private val vs1NotAlign = SrcType.isVp(io.decodedInst.srcType(0)) && RegNumNotAlign(inst.VS1, vs1Emul) 215 216 private val vs2IsMask = maskArithmeticInst || maskIndexInst 217 private val vs2IsSingleElem = redWideningInst || vmvSingleInst 218 private val vs2EewSel = Cat(lsIndexInst, (vs2WideningInst || narrowingInst || redWideningInst), intExt2, intExt4, intExt8) 219 private val vs2Eew = LookupTreeDefault(vs2EewSel, SEW, List( 220 "b10000".U -> inst.WIDTH(1, 0), 221 "b01000".U -> (SEW + 1.U), 222 "b00100".U -> (SEW - 1.U), 223 "b00010".U -> (SEW - 2.U), 224 "b00001".U -> (SEW - 3.U) 225 )) 226 private val vs2EmulSel = Cat((vs2IsMask || vs2IsSingleElem), (vs2WideningInst || narrowingInst), vmvWholeInst, (intExtInst || lsIndexInst)) 227 private val vs2Emul = LookupTreeDefault(vs2EmulSel, LMUL, List( 228 "b1000".U -> "b100".U, 229 "b0100".U -> (LMUL + 1.U), 230 "b0010".U -> NFtoLmul(inst.NF), 231 "b0001".U -> (LMUL +& vs2Eew - SEW) 232 )) 233 private val vs2NotAlign = SrcType.isVp(io.decodedInst.srcType(1)) && RegNumNotAlign(inst.VS2, vs2Emul) 234 235 private val vdIsMask = lsMaskInst || acsbInst || cmpInst || maskArithmeticInst 236 private val vdIsSingleElem = redInst || redWideningInst || vmvSingleInst 237 private val vdEew = Mux(lsStrideInst, inst.WIDTH(1, 0), Mux(vdWideningInst || redWideningInst, SEW + 1.U, SEW)) 238 private val vdEmulSel = Cat((vdIsMask || vdIsSingleElem), vdWideningInst, (lsWholeInst || vmvWholeInst), lsStrideInst) 239 private val vdEmul = LookupTreeDefault(vdEmulSel, LMUL, List( 240 "b1000".U -> "b100".U, 241 "b0100".U -> (LMUL + 1.U), 242 "b0010".U -> NFtoLmul(inst.NF), 243 "b0001".U -> (LMUL +& vdEew - SEW) 244 )) 245 private val vdNotAlign = (SrcType.isVp(io.decodedInst.srcType(2)) || io.decodedInst.vecWen) && RegNumNotAlign(inst.VD, vdEmul) 246 247 private val regNumIllegal = isVector && (vs1NotAlign || vs2NotAlign || vdNotAlign) 248 249 // 6. v0 Overlap 250 private val v0AllowOverlap = (vdIsMask || vdIsSingleElem) && !Seq(VMSBF_M, VMSIF_M, VMSOF_M).map(_ === inst.ALL).reduce(_ || _) 251 private val v0Overlap = io.decodedInst.vecWen && inst.VM === 0.U && inst.VD === 0.U && !v0AllowOverlap 252 253 // 7. Src Reg Overlap 254 private val vs1RegLo = inst.VS1 255 private val vs1RegHi = inst.VS1 +& LmultoRegNum(vs1Emul) - 1.U 256 private val vs2RegLo = inst.VS2 257 private val vs2RegHi = inst.VS2 +& LmultoRegNum(vs2Emul) - 1.U 258 private val vdRegLo = inst.VD 259 private val vdRegHi = Mux(lsStrideInst || lsIndexInst, segRegMax - 1.U, inst.VD + LmultoRegNum(vdEmul) - 1.U) 260 261 private val notAllowOverlapInst = lsIndexInst && inst.NF =/= 0.U || Seq(VMSBF_M, VMSIF_M, VMSOF_M, VIOTA_M, 262 VSLIDEUP_VX, VSLIDEUP_VI, VSLIDE1UP_VX, VFSLIDE1UP_VF, VRGATHER_VV, VRGATHEREI16_VV, VRGATHER_VX, VRGATHER_VI, VCOMPRESS_VM).map(_ === inst.ALL).reduce(_ || _) 263 264 //vs1 265 private val vs1vdRegNotOverlap = vs1RegHi < vdRegLo || vdRegHi < vs1RegLo 266 private val vs1Constraint1 = vs1IsMask && vdIsMask || !vs1IsMask && !vdIsMask && vs1Eew === vdEew 267 private val vs1Constraint2 = (vdIsMask && !vs1IsMask || !vs1IsMask && !vdIsMask && vs1Eew > vdEew) && vdRegLo === vs1RegLo && vdRegHi <= vs1RegHi 268 private val vs1Constraint3 = (!vdIsMask && vs1IsMask || !vs1IsMask && !vdIsMask && vs1Eew < vdEew) && vs1Emul >= "b100".U && vdRegHi === vs1RegHi && vdRegLo <= vs1RegLo 269 private val vs1AllowOverlap = (vs1Constraint1 || vs1Constraint2 || vs1Constraint3 || vdIsSingleElem) && !notAllowOverlapInst 270 private val vs1vdOverlap = (SrcType.isVp(io.decodedInst.srcType(0)) && io.decodedInst.vecWen) && !vs1vdRegNotOverlap && !vs1AllowOverlap 271 //vs2 272 private val vs2vdRegNotOverlap = vs2RegHi < vdRegLo || vdRegHi < vs2RegLo 273 private val vs2Constraint1 = vs2IsMask && vdIsMask || !vs2IsMask && !vdIsMask && vs2Eew === vdEew 274 private val vs2Constraint2 = (vdIsMask && !vs2IsMask || !vs2IsMask && !vdIsMask && vs2Eew > vdEew) && vdRegLo === vs2RegLo && vdRegHi <= vs2RegHi 275 private val vs2Constraint3 = (!vdIsMask && vs2IsMask || !vs2IsMask && !vdIsMask && vs2Eew < vdEew) && vs2Emul >= "b100".U && vdRegHi === vs2RegHi && vdRegLo <= vs2RegLo 276 private val vs2AllowOverlap = (vs2Constraint1 || vs2Constraint2 || vs2Constraint3 || vdIsSingleElem) && !notAllowOverlapInst 277 private val vs2vdOverlap = (SrcType.isVp(io.decodedInst.srcType(1)) && io.decodedInst.vecWen) && !vs2vdRegNotOverlap && !vs2AllowOverlap 278 279 private val regOverlapIllegal = v0Overlap || vs1vdOverlap || vs2vdOverlap 280 281 io.illegalInst := instIllegal || villIllegal || eewIllegal || emulIllegal || regNumIllegal || regOverlapIllegal 282}