vl: assign vl in csr to the value store in vl regfiles

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

show more ...

Rename: fix debug_v0_rat debug_vl_rat connection

Rename: v0 vl split

vtype: fix walk vtype value after using snapshot and the redirect siganl for vtype

vtype: add snapshot to store the vtype value in vtypebuffer and restore it when walk

Backend: add Dispatch2IqFpImp

Backend: use PipeGroupConnect between rename and dispatch stages

CtrlBlock: fix bug of fp WriteBackNums

Backend: add FpScheduler

IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)

1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

rename: optimize create snapshot (#2865)

Co-authored-by: xiao feibao <[email protected]>

CtrlBlock: fix flushVecNext enable to avoid x state

backend: new rob 8 banks read and 8 commit width

Backend: add solution for inst gpaddr

* Use ifu write gpaddr

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

show more ...

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.out(i).ready.
* Since decode promises accepting insts in order, priority encoder is used to simplify the accumulation of `numDeq`.
* `numDeq` records the number of deq insts from ibuffer, not from bypass. And it is used to update deqPtr and corresponding deqBankPtr.
* Guard numFromFetch calculation with io.in.valid to avoid updating enqPtr when input signal is invalid.
* Todo: check ibuffer timing, critical path maybe ibuffer.io.out.valid -> ibuffer.io.out.ready -> ibuffer.validEntries -> nextValidEntries -> allowEnq

show more ...

Backend: remove unused extra RF read ports, connect real commit vtype to VTypeGen

Backend: remove unused pcMem read for exu in CtrlBlock (moved to PcTargetMem (OG0))

Backend: add clock gating to valid singal

Backend: add ren signal to SyncDataModuleTemplate

Backend: add enable signal to RegNext

Backend: recover rename and dispatch pipeline