fix(Backend, Mem): add `isFromLoadUnit` to avoid other units polluting RegCache (#3731)

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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fix(Backend): connect missing `cpuHalted` signal (#3650)

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input of these modules will go through `ResetGen` and then drives the
reset of the registers inside the module.

<img
src="https://github.com/user-attachments/assets/1f544afe-4644-4604-ba6f-d14d31909f78"
width="50%">

---------
Co-authored-by: chengguanghui <[email protected]>

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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timing(LsqEnqCtrl): fix timing of lqAllocNumber and sqAllocNumber

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

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fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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timing(Backend): add OG2 stage for vector mem (#3482)

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Backend: support Shvstvala and Sstvala extension

XSCore,Backend,MemBlock: let Top-to-Backend bundles bypass MemBlock (#3398)

* All Top-to-Backend bundles are in class TopToBackendBundle.
* Including hartId, externalInterrupt, msiInfo, clintTime

XSCore,Backend,MemBlock: let Top-to-Backend bundles bypass MemBlock (#3398)

* All Top-to-Backend bundles are in class TopToBackendBundle.
* Including hartId, externalInterrupt, msiInfo, clintTime
* All Backend-to-Top bundles are in class BackendToTopBundle.
* Only cpuHalted included
* Use := instead of <> for non-Bidirectional bundles in XSCore.

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L2Top, MemBlock, Backend: reconstruct reset tree (#3333)

Modules in XSTile are reset in the order of L2, MemBlock, Backend and
Frontend.

<img
src="https://github.com/user-attachments/assets/ae9

L2Top, MemBlock, Backend: reconstruct reset tree (#3333)

Modules in XSTile are reset in the order of L2, MemBlock, Backend and
Frontend.

<img
src="https://github.com/user-attachments/assets/ae927496-9d4d-45fc-a924-78be181d4fa7"
width="40%">

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Backend: Check that instruction is load when load exus write back to the reg cache. Some atomic instructions also write back through the load exus

BypassNetwork: add source data from RegCache

Backend: add reg cache data writing back path

DataPath: add RegCache

CSR: remove useless distributedUpdate

Redirect fix timing (#3209)

Backend: pipe fromTop's clintTime and msiInfo for fix timing (#3262)

Backend: optimize og0 cancel signals (#3235)

* use Vec[Bool] instead of UInt for og0Cancel
* only wakeup source Exus containing 0-latency function unit should send
og0Cancel

DataPath, BusyTable: remove unnecessary cancel signals (#3218)

* only non-load wakeup sources exu should send og0cancel
* og0cancel only works on the wakeup of 0 latency instructions