pass reset vector from SimTop (#1545)

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. Aft

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

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bump huancun (#1466)

* bump huancun

* bump huancun

* bump huancun

* Insert 1 buffer betwwen L2 and L3

Co-authored-by: LinJiawei <[email protected]>

Adjusted reset signals (#1441)

* Adjusted reset signals

* Support reset tree

Connect L2 ecc error to BEU / Connect L3 ecc error to PLIC (#1415)

* l2/l3: Report ecc error to beu or plic

* Bump huancun

* Connect l3 ecc error to plic

mem: split L1CacheErrorInfo and L1BusErrorUnitInfo, fix ecc error (#1409)

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem:

mem: split L1CacheErrorInfo and L1BusErrorUnitInfo, fix ecc error (#1409)

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

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mem: refactor l1 error implementation (#1391)

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send f

mem: refactor l1 error implementation (#1391)

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: JinYue <[email protected]>

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SoC: insert more buffers into mmio path (#1329)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl

SoC: insert more buffers into mmio path (#1329)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: fix write mask for mstatus, mepc and sepc

This commit fixes the write mask for mstatus, mepc and sepc.

According to the RISC-V instruction manual, for RV64 systems,
the SXL and UXL fields are WARL fields that control the value of
XLEN for S-mode and U-mode, respectively. For RV64 systems, if
S-mode is not supported, then SXL is hardwired to zero. For RV64
systems, if U-mode is not supported, then UXL is hardwired to zero.

Besides, mepc[0] and sepc[0] should be hardwired to zero.

* wb,load: delay load fp for one cycle

* csr: add mconfigptr, but hardwire to 0 now

* bump huancun

* csr: add *BE to mstatusStruct which are hardwired to 0

* Remove unused files

* csr: fix bug of xret clear mprv

* bump difftest

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

* mem,atomics: delay exception info for one cycle

* SoC: insert more buffers into mmio path

* SoC: insert buffer between l3_xbar and l3_banked_xbar

* Optimze l3->ddr path

* Bump huancun

Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for peripheral port

* Fix submodule version

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SoC timing fix (#1253)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

Fix multi-core dedup bug (#1235)

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

SoC: change buffer latency && set L3 size to 8MB (#1205)

* SoC: change buffer latency && set L3 size to 8MB

* BinaryArbiter: fix bugs when iknow < 4

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams t

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

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Config update (#1164)

* Bump HuanCun
* Increase L2/L3 latency
* Change 10MB L3 to default config
* Bump difftest

add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

misc: do bug fix (#1157)

* bump difftest & huancun

misc: put reset signals in a chain (#1147)

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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