xref: /XiangShan/src/main/scala/xiangshan/XSTile.scala (revision 0f59c834b79b456c9fca10e45f2d6b66cf33d136) 
1package xiangshan
2
3import chisel3._
4import chipsalliance.rocketchip.config.{Config, Parameters}
5import chisel3.util.{Valid, ValidIO}
6import freechips.rocketchip.diplomacy.{BundleBridgeSink, LazyModule, LazyModuleImp, LazyModuleImpLike}
7import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
8import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple}
9import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
10import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLNode, TLTempNode, TLXbar}
11import huancun.debug.TLLogger
12import huancun.{HCCacheParamsKey, HuanCun}
13import system.HasSoCParameter
14import top.BusPerfMonitor
15import utils.{ResetGen, TLClientsMerger, TLEdgeBuffer}
16
17class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
18  val ecc_error = Valid(UInt(soc.PAddrBits.W))
19}
20
21class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
22  val icache = new L1BusErrorUnitInfo
23  val dcache = new L1BusErrorUnitInfo
24
25  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
26    List(
27//      Some(icache.paddr, s"IBUS", s"Icache bus error"),
28      Some(icache.ecc_error, s"I_ECC", s"Icache ecc error"),
29//      Some(dcache.paddr, s"DBUS", s"Dcache bus error"),
30      Some(dcache.ecc_error, s"D_ECC", s"Dcache ecc error")
31    )
32}
33
34/**
35  *   XSTileMisc contains every module except Core and L2 Cache
36  */
37class XSTileMisc()(implicit p: Parameters) extends LazyModule
38  with HasXSParameter
39  with HasSoCParameter
40{
41  val l1_xbar = TLXbar()
42  val mmio_xbar = TLXbar()
43  val mmio_port = TLIdentityNode() // to L3
44  val memory_port = TLIdentityNode()
45  val beu = LazyModule(new BusErrorUnit(
46    new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode
47  ))
48  val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
49  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform)
50  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
51
52  val i_mmio_port = TLTempNode()
53  val d_mmio_port = TLTempNode()
54
55  busPMU := l1d_logger
56  l1_xbar :=* busPMU
57
58  l2_binder match {
59    case Some(binder) =>
60      memory_port := TLBuffer() := TLClientsMerger() := TLXbar() :=* binder
61    case None =>
62      memory_port := l1_xbar
63  }
64
65  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
66  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
67  beu.node := TLBuffer.chainNode(1) := mmio_xbar
68  mmio_port := TLBuffer() := mmio_xbar
69
70  lazy val module = new LazyModuleImp(this){
71    val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors)))
72    beu.module.io.errors <> beu_errors
73  }
74}
75
76class XSTile()(implicit p: Parameters) extends LazyModule
77  with HasXSParameter
78  with HasSoCParameter
79{
80  private val core = LazyModule(new XSCore())
81  private val misc = LazyModule(new XSTileMisc())
82  private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
83    LazyModule(new HuanCun()(new Config((_, _, _) => {
84      case HCCacheParamsKey => l2param
85    })))
86  )
87
88  // public ports
89  val memory_port = misc.memory_port
90  val uncache = misc.mmio_port
91  val clint_int_sink = core.clint_int_sink
92  val plic_int_sink = core.plic_int_sink
93  val debug_int_sink = core.debug_int_sink
94  val beu_int_source = misc.beu.intNode
95  val core_reset_sink = BundleBridgeSink(Some(() => Bool()))
96
97  if (coreParams.dcacheParametersOpt.nonEmpty) {
98    misc.l1d_logger :=
99      TLBuffer.chainNode(1, Some("L1D_to_L2_buffer")) :=
100      core.memBlock.dcache.clientNode
101  }
102  misc.busPMU :=
103    TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
104    TLBuffer.chainNode(1, Some("L1I_to_L2_buffer")) :=
105    core.frontend.icache.clientNode
106
107  if (!coreParams.softPTW) {
108    misc.busPMU :=
109      TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
110      TLBuffer.chainNode(3, Some("PTW_to_L2_buffer")) :=
111      core.ptw.node
112  }
113  l2cache match {
114    case Some(l2) =>
115      misc.l2_binder.get :*= l2.node :*= TLBuffer() :*= misc.l1_xbar
116    case None =>
117  }
118
119  misc.i_mmio_port := core.frontend.instrUncache.clientNode
120  misc.d_mmio_port := core.memBlock.uncache.clientNode
121
122  lazy val module = new LazyModuleImp(this){
123    val io = IO(new Bundle {
124      val hartId = Input(UInt(64.W))
125    })
126
127    dontTouch(io.hartId)
128
129    val core_soft_rst = core_reset_sink.in.head._1
130
131    core.module.io.hartId := io.hartId
132    if(l2cache.isDefined){
133      core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2)
134    }
135    else {
136      core.module.io.perfEvents <> DontCare
137    }
138
139    misc.module.beu_errors <> core.module.io.beu_errors
140
141    // Modules are reset one by one
142    // io_reset ----
143    //             |
144    //             v
145    // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
146    val l2cacheMod = if (l2cache.isDefined) Seq(l2cache.get.module) else Seq()
147    val resetChain = Seq(
148      Seq(misc.module, core.module) ++ l2cacheMod
149    )
150    ResetGen(resetChain, reset.asBool || core_soft_rst, !debugOpts.FPGAPlatform)
151  }
152}
153