RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
-

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
- bug fixes
- timing fixes
- SRAM-Queue | https://github.com/OpenXiangShan/CoupledL2/pull/228
- data SRAM splitted into 4 |
https://github.com/OpenXiangShan/CoupledL2/pull/229

---------

Co-authored-by: lixin <[email protected]>

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L2Top, MemBlock, Backend: reconstruct reset tree (#3333)

Modules in XSTile are reset in the order of L2, MemBlock, Backend and
Frontend.

<img
src="https://github.com/user-attachments/assets/ae9

L2Top, MemBlock, Backend: reconstruct reset tree (#3333)

Modules in XSTile are reset in the order of L2, MemBlock, Backend and
Frontend.

<img
src="https://github.com/user-attachments/assets/ae927496-9d4d-45fc-a924-78be181d4fa7"
width="40%">

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l2pf: add pmp resp

Backend,XSTop: connect clint time to CSR

IMSIC: update verilog module and io

NewCSR: add IMSIC

SoC: an initial version of DummyLLC

coupledL2, L2Top, XSTile: refactor CoupledL2 top-level framework (#3022)

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect down

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect downstream interconnect. The key features of TL2CHICoupledL2
are:
* Fully coherent Request Node in a CHI interconnect.
* Coherency granule of 64B cache line.
* MESI cache coherence model, which is based on TileLink coherence
policies.
* Transition from TL-C transactions to CHI snoopable requests.
* Transition from TL-UL transactions to CHI non-snoopable requests.
* Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique.
* Support for WriteNoSnp, WriteBackFull, Evict.
* Support for all the snoops except for SnpDVMOp.
* Request retry to manage protocol resources.
* Message transfer across CHI interfaces based on Link Layer Credit.
* Power aware signaling on the component interface.

The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2
still works as default L2 Cache instance in
[XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for
now. TL2CHICoupledL2 is still not available for verilator simulation in
this pr.

To compile XSTile verilog with TL2CHICoupledL2, run `make verilog
CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Zhu Yu <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

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l2bop: train by virtual address and buffer tlb req (#2382)

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

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Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming

fix merge error

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(add isKeyword)

*DCacheWrapper: add lqidx for compare age, add IsKeywordField

*LoadPipe: add lqIdx for miss_req

*MissQueue: add "isKeyword" logic for miss entries, MissReqPipeReg
transfer "isKeyword" from L1 to L2 by mem_acquire
modify refill_to_ldq 's addr/data logic depending on
"isKeyword"
modify load forward data from mshr logic

*LoadQueueReplay: modify replay order by l2_hint

*LoadUnit: add lqIdx in dcache_req

* modify iskeyword 'user' to 'echo', load forward data from tlbundle D

* L2TOP: modify l2_hint type, add l2_hint_iskeyword

* LRQ: add l2_hint xsperf counter

* modify merge conflict:
loadunit: name changed so_uop --> so_select_src.uop

* DCacheWrapper: modify tl_channel_D 2 beats both can fwd data

* dump coupledL2 : Feature favor l1 d keyword priority (#87)

* Fix fma rm (#2586)

* bump fudian

* fma: fix bug of fadd's rm

* FMA: fix bug of fadd's rm

* dump : coupledL2 branch:feature-favor-L1D-keyword-priority

* dump coupledL2

---------

Co-authored-by: xiaofeibao-xjtu <[email protected]>

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Merge remote-tracking branch 'upstream/master' into backendq

Move one buffer in L1I - L2 path from L2Top to MemBlock (#2505)

Merge timing fixes of XSTile into Master (#2488)

* Timing: add buffer in Frontend-L2 path
double buffer applied in icache-L2 (both at MemBlock)
single buffer applied in frontend-MMIO (at MemBlock)

Merge timing fixes of XSTile into Master (#2488)

* Timing: add buffer in Frontend-L2 path
double buffer applied in icache-L2 (both at MemBlock)
single buffer applied in frontend-MMIO (at MemBlock)

* Move l1d-to-l2 buffer from L2Top to MemBlock to balance timing

* Use arcane methods to keep Frontend MMIO port name for MemBlock

* Add Reg for L2-L1 Hint in both L2Top and MemBlock

* Add Buffer between l1_xbar and L2

* Add buffer for beu_error in MemBlock

* Frontend: add buffer for reset_vector in Frontend-memBlock path (by ssszwic)

* Move one buffer in L1-L2 from MemBlock to L2Top

* Add another buffer in frontend MMIO path

* Fix compilation error

* Hint revert to master design, the Reg here is canceled because we have this reg in L2

* Add a third buffer in I-MMIO path

* Add a third buffer in PTW-L2 path at L2Top(above xbar)

* Fix I-mmio buffer constant values wrongly assigned

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Support ctrl/meta-decoupled TP (#2407)

* bump huancun

* bump coupledL2

* top,tile: support ctrl/meta-decoupled temporal prefetcher

* bump utility

* bump huancun

* bump coupledL2

*

Support ctrl/meta-decoupled TP (#2407)

* bump huancun

* bump coupledL2

* top,tile: support ctrl/meta-decoupled temporal prefetcher

* bump utility

* bump huancun

* bump coupledL2

* top: add broadcast between tp-ctrl&tp-meta

* config: assert L2 cache as inclusive

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XSTile partition (#2390)

This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock

XSTile partition (#2390)

This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock and all the interfaces from core to tile will go through MemBlock.

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fix merge error

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

LazyModule: do not inline lazy modules in XS (#2311)