1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import org.chipsalliance.cde.config.{Config, Parameters} 21import chisel3.util.{Valid, ValidIO} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import coupledL2.{L2ParamKey, CoupledL2} 27import system.HasSoCParameter 28import top.BusPerfMonitor 29import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 30 31class XSTile()(implicit p: Parameters) extends LazyModule 32 with HasXSParameter 33 with HasSoCParameter 34{ 35 override def shouldBeInlined: Boolean = false 36 private val core = LazyModule(new XSCore()) 37 private val l2top = LazyModule(new L2Top()) 38 39 // =========== Public Ports ============ 40 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt 41 val memory_port = l2top.memory_port 42 val uncache = l2top.mmio_port 43 val beu_int_source = l2top.beu.intNode 44 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 45 val clint_int_node = l2top.clint_int_node 46 val plic_int_node = l2top.plic_int_node 47 val debug_int_node = l2top.debug_int_node 48 core.memBlock.clint_int_sink := clint_int_node 49 core.memBlock.plic_int_sink :*= plic_int_node 50 core.memBlock.debug_int_sink := debug_int_node 51 52 // =========== Components' Connection ============ 53 // L1 to l1_xbar 54 coreParams.dcacheParametersOpt.map { _ => 55 l2top.misc_l2_pmu := l2top.l1d_logger := core.memBlock.dcache_port := 56 core.memBlock.l1d_to_l2_buffer.node := core.memBlock.dcache.clientNode 57 } 58 59 l2top.misc_l2_pmu := l2top.l1i_logger := core.memBlock.frontendBridge.icache_node 60 if (!coreParams.softPTW) { 61 l2top.misc_l2_pmu := l2top.ptw_logger := l2top.ptw_to_l2_buffer.node := core.memBlock.ptw_to_l2_buffer.node 62 } 63 l2top.l1_xbar :=* l2top.misc_l2_pmu 64 65 val l2cache = l2top.l2cache 66 // l1_xbar to l2 67 l2cache match { 68 case Some(l2) => 69 l2.node :*= l2top.xbar_l2_buffer :*= l2top.l1_xbar 70 l2.pf_recv_node.map(recv => { 71 println("Connecting L1 prefetcher to L2!") 72 recv := core.memBlock.l2_pf_sender_opt.get 73 }) 74 case None => 75 } 76 77 val core_l3_tpmeta_source_port = l2cache match { 78 case Some(l2) => l2.tpmeta_source_node 79 case None => None 80 } 81 val core_l3_tpmeta_sink_port = l2cache match { 82 case Some(l2) => l2.tpmeta_sink_node 83 case None => None 84 } 85 86 // mmio 87 l2top.i_mmio_port := l2top.i_mmio_buffer.node := core.memBlock.frontendBridge.instr_uncache_node 88 l2top.d_mmio_port := core.memBlock.uncache.clientNode 89 90 // =========== IO Connection ============ 91 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 92 val io = IO(new Bundle { 93 val hartId = Input(UInt(hartIdLen.W)) 94 val reset_vector = Input(UInt(PAddrBits.W)) 95 val cpu_halt = Output(Bool()) 96 val debugTopDown = new Bundle { 97 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 98 val l3MissMatch = Input(Bool()) 99 } 100 }) 101 102 dontTouch(io.hartId) 103 104 val core_soft_rst = core_reset_sink.in.head._1 // unused 105 106 l2top.module.hartId.fromTile := io.hartId 107 core.module.io.hartId := l2top.module.hartId.toCore 108 core.module.io.reset_vector := l2top.module.reset_vector.toCore 109 l2top.module.reset_vector.fromTile := io.reset_vector 110 l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt 111 io.cpu_halt := l2top.module.cpu_halt.toTile 112 113 if (l2cache.isDefined) { 114 // TODO: add perfEvents of L2 115 // core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2) 116 core.module.io.perfEvents <> DontCare 117 } 118 else { 119 core.module.io.perfEvents <> DontCare 120 } 121 122 l2top.module.beu_errors.icache <> core.module.io.beu_errors.icache 123 l2top.module.beu_errors.dcache <> core.module.io.beu_errors.dcache 124 if (l2cache.isDefined) { 125 // TODO: add ECC interface of L2 126 127 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 128 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 129 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 130 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 131 132 core.module.io.l2PfqBusy := false.B 133 core.module.io.debugTopDown.l2MissMatch := l2top.module.debugTopDown.l2MissMatch 134 l2top.module.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 135 } else { 136 137 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 138 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 139 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 140 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 141 142 core.module.io.l2PfqBusy := false.B 143 core.module.io.debugTopDown.l2MissMatch := false.B 144 } 145 146 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 147 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 148 149 // Modules are reset one by one 150 // io_reset ---- 151 // | 152 // v 153 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores} 154 // val resetChain = Seq( 155 // Seq(l2top.module, core.module) 156 // ) 157 // ResetGen(resetChain, reset, !debugOpts.FPGAPlatform) 158 } 159 160 lazy val module = new XSTileImp(this) 161} 162