| #
faf3cfa9 |
| 22-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] fix ftq update logic
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| #
36d7aed5 |
| 21-Jan-2021 |
LinJiawei <[email protected]> |
FTQ: impl ftq
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| #
2e947747 |
| 21-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] update Cfiupdate
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| #
b97160fe |
| 21-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] update FtqEntry
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| #
c778d2af |
| 21-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] update frontend interface
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| #
f606cf17 |
| 20-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] remove brq form backend
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| #
884dbb3b |
| 20-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] connect Ftq into ctrl block
|
| #
8a5e9243 |
| 20-Jan-2021 |
LinJiawei <[email protected]> |
[WIP] add fetch packet into 'FrontendToBackendIO' and ftq io
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| #
7447ee13 |
| 20-Jan-2021 |
Lingrui98 <[email protected]> |
ras: move RASEntry to top level
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| #
51b2a476 |
| 20-Jan-2021 |
zoujr <[email protected]> |
Perf: Add counter for predictors
|
| #
ec778fd0 |
| 20-Jan-2021 |
Lingrui98 <[email protected]> |
bundle: add OfqEntry
|
| #
d63f8278 |
| 18-Jan-2021 |
Yinan Xu <[email protected]> |
Merge branch 'master' into perf-debug
|
| #
e9dac0fe |
| 16-Jan-2021 |
zoujr <[email protected]> |
Merge remote-tracking branch 'origin/fix-sdcard' into perf-debug
|
| #
7d793c5a |
| 16-Jan-2021 |
zoujr <[email protected]> |
Perf: Add BPU pred pref counter
|
| #
735cbcf4 |
| 16-Jan-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-queue-data
|
| #
0bc5da93 |
| 15-Jan-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into perf-debug
|
| #
070fc25d |
| 15-Jan-2021 |
ljw <[email protected]> |
Merge branch 'master' into opt-imm-pc
|
| #
3949bd84 |
| 14-Jan-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-queue-data
|
| #
baf8def6 |
| 14-Jan-2021 |
Yinan Xu <[email protected]> |
exceptionVec: use Vec(16, Bool()) for ExceptionVec()
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| #
7ec59831 |
| 14-Jan-2021 |
wangkaifan <[email protected]> |
Merge branch 'master' of https://github.com/RISCVERS/XiangShan into perfcnt
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| #
8635f18f |
| 14-Jan-2021 |
wangkaifan <[email protected]> |
csr: support perfcnt CSRs & skip difftest for them
* values of hardware performance counters can hardly be emulated by NEMU
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| #
b0ae3ac4 |
| 14-Jan-2021 |
LinJiawei <[email protected]> |
Opt imm: save imm in 20-bit space
|
| #
fd69e556 |
| 12-Jan-2021 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into perf-debug
|
| #
9d9af70a |
| 10-Jan-2021 |
jinyue110 <[email protected]> |
Merge branch 'master' into ifu-pakcet-aligned
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| #
576af497 |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
ifu, bpu: totally remove the concept of 'bank'
|