Trigger: refactor trigger information in pipeline. (#3403)

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

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RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

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Co-authored-by: xiaofeibao <[email protected]>

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RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

LDU, Decode: add support for software prefetch (Zicbop) (#3356)

1. Support RVA23 SoftPrefetch instructions, include prefetch.i ,
prefetch.w and prefetch.r.
2. In DecodeUnit, add decode of SoftPref

LDU, Decode: add support for software prefetch (Zicbop) (#3356)

1. Support RVA23 SoftPrefetch instructions, include prefetch.i ,
prefetch.w and prefetch.r.
2. In DecodeUnit, add decode of SoftPrefetch.
3. prefetch.i ,prefetch.w and prefetch.r will be dispatched into
load-pipe, and then prefetch.w and prefetch.r execute like a load.
4. preftch.i just calculate address in loadUnit, then transfer address
to Frontend.(TODO)
5. All SoftPrefetch instructions return “ldout” signals to Backend in
stage3 wether hit or miss.

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Redirect fix timing (#3209)

RAS: modify the NOS pointer write value during redirection (#3237)

Fix NOS update error when redirecting ret instruction, and correct the
bit width of sctr.

Trigger: add breakpoint exception for `STORE`

*prevent `STORE` from writing sbuffer when trigger fire.

CSR: remove the enable bit for `svinval` extension

* Since `svinval` extension has been merged into the risc-v specification, there is no need to use custom config to disable it.

NewCSR: Refactor CSR about Debug

* add CSR: trigger csr & debug csr

* add CSR event: TrapEntryDEvent & DretEvent

* fixed trigger's comparison func between Consecutive pc and tdada2

NewCSR: fix tlb connection

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
w

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
widths of all read/write ports were set to 6, which works well but is
not parameterized. Now these widths are modified to be controlled by
parameters.

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L1CacheErrorInfo: code refactor for correct and convenient clockgate (#3044)

ResetPregStateReq: add isV0 isVl

Rename: v0 vl split

L1Cache: L1CacheError must be valid to report to beu (#3011)

`L1CacheErrorInfo.report_to_beu` is valid iff `L1CacheErrorInfo.valid === true.B`,
therefore `beu_errors.[id]cache.valid` should be `val

L1Cache: L1CacheError must be valid to report to beu (#3011)

`L1CacheErrorInfo.report_to_beu` is valid iff `L1CacheErrorInfo.valid === true.B`,
therefore `beu_errors.[id]cache.valid` should be `valid && report_to_beu`.

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Merge branch 'master' into vlsu-merge-master-0504

CSR: remove useless sdsid custom-CSR (#2980)

Custom-CSR sdsid is a legacy from labeled XiangShan, which is no longer
in use. Remove this Custom-CSR.

This patch fixes OpenXiangShan/NEMU#329

Merge branch 'master' into vlsu-merge-master-0504

ftq: cut area of ftq_redirect_mem (#2856)

dlt folded_hist/afhob/lastBrNumOH
ftq_redirect_mem: 247*64->73*64

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: sc

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS

ftq_redirect_sram->ftq_redirect_mem

Co-authored-by: chenguokai <[email protected]>

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Backend: add FpScheduler

IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)

1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured

Merge branch 'master' into vlsu-tmp-master