History log of /XiangShan/src/main/scala/top/XSNoCTop.scala (Results 26 – 35 of 35)
Revision Date Author Comments
# 9143e232 12-Sep-2024 Jiuyue Ma <[email protected]>

feat(IMSIC): combine M/S mode axi4lite ports into single port (#3519)

Signed-off-by: Jiuyue Ma <[email protected]>


# b30cb8bf 11-Sep-2024 Guanghui Cheng <[email protected]>

fix(XSNoCTop): add port `hartIsInReset` for StandAloneDebugModule. (#3538)


# 69652e6e 09-Sep-2024 Tang Haojin <[email protected]>

fix(XSNoCTop): do not generate noc_clock without CHIAsyncBridge (#3516)


# e2725c9e 01-Sep-2024 zhanglinjuan <[email protected]>

SoC, XSNoCTop, XSTileWrap: add switch for the async bridges (#3459)


# 0700cab2 21-Aug-2024 Tang Haojin <[email protected]>

Top: set the width of `riscv_rst_vec` to PaddrBits (#3410)


# 8537b88a 20-Aug-2024 Tang Haojin <[email protected]>

Top: add XSTileWrap for async signals (#3400)

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: zhaohong1988 <[email protected]>


# 2f9ea954 06-Aug-2024 Tang Haojin <[email protected]>

XSNoCTop, StandAloneDevice: add async signal handling (#3321)


# 6cb0b9a3 10-Jul-2024 sinceforYy <[email protected]>

XSNoCTop: fix IO Bundle to generate XSNocTop verilog file


# bb2f3f51 12-Jul-2024 Tang Haojin <[email protected]>

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

show more ...


# 720dd621 04-Jul-2024 Tang Haojin <[email protected]>

top: implement XSNoCTop and standalone devices (#3136)


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