fix: sync the signals before use for lowpower (#4610)

fix(top): enable cpuclock when debug halt req (#4583)

fix: add low power related logic (#4554)

refactor(DFT): refactor `DFT` IO (#4530)

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the c

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the clock

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feat(AIA): integrate ChiselAIA again (#4509)

chore(XSNoCTop): change to dft and dft_reset io (#4502)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoo

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoop.
* low-power process is controlled by FSM to follow the steps: flush L2
-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)
* SoC plays as PPU to generate power on/off sequence with signals:
isolation/reset/clock, also the power on/off req/ack signals

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chore: fix several deprecation warning (#4352)

feat(AIA): integrate ChiselAIA (#4378)

feat(dfx): integerate dfx components (#4312)

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/d

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/difftest IOs.

Currently we use two-step flow for CHI-NoC-XS as follow:
Step1. Generate single-core XSNoCDiffTop with JsonProfile,
which support generate another DifftestEndpoint seperately.
Step2. Generate n-core Difftest according to JsonProfile
Step3. Connect XS and Difftest manually or by some scripts.

As XSNoCDiffTop is only part of Difftest, we collect PerfCounters
for each DiffTop, need control signals passed from Outer module.
And to avoid potential connection problem, we add checker module
and CI test.

To maintain compatibility with previous IT/ST flow, we extend
XSNoCDiffTopConfig to enable difftest wrapper.

An example usage:
make verilog PLDM=1 PLDM_ARGS="--difftest-config H" CONFIG=XSNoCDiffTopConfig

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feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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feat(DM, hartReset): support `hartReset` which could reset selected harts

* Add hartResetReq in XSNocTop.
* Support `hartReset` features

fix(trace): add pipe for traceCoreInterface in memblock and l2top

feat(trace): add TraceCoreInterface in top.

feat(dbltrp) : add support for critical error (#3793)

fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

feat(Synchronizer): use unified AsyncResetSynchronizerShiftReg (#3609)

fix(XSNoCTop): add missing module prefix functionality (#3581)

fix(XSNoCTop): remove noc_reset_sync when CHIAsyncBridge is disabled (#3573)