xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision 8e93c8f6627b24bf600af40f26ae8f72d2f0cd48) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
34import chisel3.experimental.{annotate, ChiselAnnotation}
35import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
36
37class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
38{
39  override lazy val desiredName: String = "XSTop"
40
41  ResourceBinding {
42    val width = ResourceInt(2)
43    val model = "freechips,rocketchip-unknown"
44    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
45    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
46    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
47    Resource(ResourceAnchors.root, "width").bind(width)
48    Resource(ResourceAnchors.soc, "width").bind(width)
49    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
50    def bindManagers(xbar: TLNexusNode) = {
51      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
52        manager.resources.foreach(r => r.bind(manager.toResource))
53      }
54    }
55  }
56
57  require(enableCHI)
58
59  // xstile
60  val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
61    case XSCoreParamsKey => tiles.head
62    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
63  })))
64
65  // imsic bus top
66  val u_imsic_bus_top = LazyModule(new imsic_bus_top(
67    useTL = soc.IMSICUseTL,
68    baseAddress = (0x3A800000, 0x3B000000)
69  ))
70
71  // interrupts
72  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
73  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
74  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
75  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
76  core_with_l2.clintIntNode := clintIntNode
77  core_with_l2.debugIntNode := debugIntNode
78  core_with_l2.plicIntNode :*= plicIntNode
79  beuIntNode := IntBuffer(2) := core_with_l2.tile.beu_int_source
80  val clint = InModuleBody(clintIntNode.makeIOs())
81  val debug = InModuleBody(debugIntNode.makeIOs())
82  val plic = InModuleBody(plicIntNode.makeIOs())
83  val beu = InModuleBody(beuIntNode.makeIOs())
84
85  // reset nodes
86  val core_rst_node = BundleBridgeSource(() => Reset())
87  core_with_l2.tile.core_reset_sink := core_rst_node
88
89  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
90    soc.XSTopPrefix.foreach { prefix =>
91      val mod = this.toNamed
92      annotate(new ChiselAnnotation {
93        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
94      })
95    }
96    FileRegisters.add("dts", dts)
97    FileRegisters.add("graphml", graphML)
98    FileRegisters.add("json", json)
99    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
100
101    val clock = IO(Input(Clock()))
102    val reset = IO(Input(AsyncReset()))
103    val noc_clock = EnableCHIAsyncBridge.map(_ => IO(Input(Clock())))
104    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
105    val soc_clock = IO(Input(Clock()))
106    val soc_reset = IO(Input(AsyncReset()))
107    val io = IO(new Bundle {
108      val hartId = Input(UInt(p(MaxHartIdBits).W))
109      val riscv_halt = Output(Bool())
110      val hartIsInReset = Output(Bool())
111      val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
112      val chi = new PortIO
113      val nodeID = Input(UInt(soc.NodeIDWidthList(issue).W))
114      val clintTime = Input(ValidIO(UInt(64.W)))
115    })
116    // imsic axi4lite io
117    val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
118    // imsic tl io
119    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
120    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
121
122    val reset_sync = withClockAndReset(clock, reset) { ResetGen() }
123    val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen() })
124    val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
125
126    // override LazyRawModuleImp's clock and reset
127    childClock := clock
128    childReset := reset_sync
129
130    // device clock and reset
131    wrapper.u_imsic_bus_top.module.clock := soc_clock
132    wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
133
134    // imsic axi4lite io connection
135    wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
136
137    // imsic tl io connection
138    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
139    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
140
141    // input
142    dontTouch(io)
143
144    core_with_l2.module.io.hartId := io.hartId
145    core_with_l2.module.io.nodeID.get := io.nodeID
146    io.riscv_halt := core_with_l2.module.io.cpu_halt
147    io.hartIsInReset := core_with_l2.module.io.hartIsInReset
148    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
149
150    EnableClintAsyncBridge match {
151      case Some(param) =>
152        val source = withClockAndReset(soc_clock, soc_reset_sync) {
153          Module(new AsyncQueueSource(UInt(64.W), param))
154        }
155        source.io.enq.valid := io.clintTime.valid
156        source.io.enq.bits := io.clintTime.bits
157        core_with_l2.module.io.clintTime.get <> source.io.async
158      case None =>
159        core_with_l2.module.io.clintTime.get <> io.clintTime
160    }
161
162    EnableCHIAsyncBridge match {
163      case Some(param) =>
164        val sink = withClockAndReset(noc_clock.get, noc_reset_sync.get) {
165          Module(new CHIAsyncBridgeSink(param))
166        }
167        sink.io.async <> core_with_l2.module.io.chi.get
168        io.chi <> sink.io.deq
169      case None =>
170        io.chi <> core_with_l2.module.io.chi.get
171    }
172
173    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
174    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
175    // tie off core soft reset
176    core_rst_node.out.head._1 := false.B.asAsyncReset
177
178    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
179
180    withClockAndReset(clock, reset_sync) {
181      // Modules are reset one by one
182      // reset ----> SYNC --> Core
183      val resetChain = Seq(Seq(core_with_l2.module))
184      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
185    }
186
187  }
188
189  lazy val module = new XSNoCTopImp(this)
190}
191