Top: add XSTileWrap for async signals (#3400)

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: zhaohong1988 <[email protected]>

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

SoC: add buffer between AXI4Xbar and CLINT

CLINT for simulation echoes response in the same cycle as the request.
However, AXI4Xbar is unable to handle synchronous response because
AXI4Xbar must tra

SoC: add buffer between AXI4Xbar and CLINT

CLINT for simulation echoes response in the same cycle as the request.
However, AXI4Xbar is unable to handle synchronous response because
AXI4Xbar must track id flow.

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Backend,XSTop: connect clint time to CSR

NewCSR: add IMSIC

top: implement XSNoCTop and standalone devices (#3136)

SoC, Top: use Option for SoC widgets concerning L3

SoC: an initial version of DummyLLC

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect down

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect downstream interconnect. The key features of TL2CHICoupledL2
are:
* Fully coherent Request Node in a CHI interconnect.
* Coherency granule of 64B cache line.
* MESI cache coherence model, which is based on TileLink coherence
policies.
* Transition from TL-C transactions to CHI snoopable requests.
* Transition from TL-UL transactions to CHI non-snoopable requests.
* Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique.
* Support for WriteNoSnp, WriteBackFull, Evict.
* Support for all the snoops except for SnpDVMOp.
* Request retry to manage protocol resources.
* Message transfer across CHI interfaces based on Link Layer Credit.
* Power aware signaling on the component interface.

The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2
still works as default L2 Cache instance in
[XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for
now. TL2CHICoupledL2 is still not available for verilator simulation in
this pr.

To compile XSTile verilog with TL2CHICoupledL2, run `make verilog
CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Zhu Yu <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

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soc: remove extra assignment to rtcTick (#2839)

clint.module.io.rtcTick should be driven by rtc_clock. This
commit removes the extra assignment.

Makefile: `XSTOP_PREFIX` for nested prefix of `XSTop` (#2799)

* This does not work for chisel 3

Add a new AXI4UserYanker node to fix 4 core bug (#2384)

Bump rocket-chip (#2353)

SoC: require the ReqSourceKey user bits at top (#2357)

The top-level memory port requires the ReqSourceKey user bits.

This would avoid adding an extra key through the BusPerfMonitor and
also ben

SoC: require the ReqSourceKey user bits at top (#2357)

The top-level memory port requires the ReqSourceKey user bits.

This would avoid adding an extra key through the BusPerfMonitor and
also benefit SoC level optimizations, such as system caches.

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chore: remove deprecated brackets, APIs, etc. (#2321)

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump hua

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

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top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache wri

Uncache: optimize write operation (#1844)

This commit adds an uncache write buffer to accelerate uncache write

For uncacheable address range, now we use atomic bit in PMA to indicate
uncache write in this range should not use uncache write buffer.

Note that XiangShan does not support atomic insts in uncacheable address range.

* uncache: optimize write operation

* pma: add atomic config

* uncache: assign hartId

* remove some pma atomic

* extend peripheral id width

Co-authored-by: Lyn <[email protected]>

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soc: external interrupts should be level-triggered

soc: add synchronizers for external interrupt bits (#1566)

soc: fix implementation of rtc_clock (#1565)

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle

soc: fix implementation of rtc_clock (#1565)

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle in io_clock for every cycle in rtc_clock. We add sampling
registers in this commit to fix this.

show more ...

top: add real-time clock for CLINT (#1553)

SoC: remove error_xbar; add more buffers (#1454)

* SoC: remove error_xbar; add more buffers

* Bump huancun

* Misc: set timeout threshold to 10000 cycles

* Bump huancun

SoC: timing opt (#1431)

* SoC: timing opt

* Added buffers for pma

Co-authored-by: Yinan Xu <[email protected]>