Bump difftest (#2391)

* use the abstract DifftestMem class
* move DifftestModule.finish to hardware

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

sim: add AXI4 memory slave model in Chisel (#1799)

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

use ExtModule instead of Chisel3.BlackBox. (#988)

Bump chisel to 3.5 (#974)

* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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AXI4RAM: enable when state === s_wdata

ram: support memory larger than 2GiB

ram: allow larger ram

ram_helper: add enable

AXI4RAM: fixed rIdx and wIdx.
Now, we can pass coremark.

AXI4RAM: make beatBytes fully parameterized.
When beatBytes > 8, we split it into multiple 64bit RAMHelper.

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G,

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

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Fix axi device bug

Add 'memByte' arg to AXIRAM

Rewrite AXI4Ram

utils: add MaskExpand()

refactor AddrBits and DataBits for the whole system

Merge branch 'master' into dev-rv64