1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.experimental.ExtModule 23import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4SlaveNode} 24import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp, RegionType} 25import utils.MaskExpand 26 27class RAMHelper(memByte: BigInt) extends ExtModule { 28 val DataBits = 64 29 30 val clk = IO(Input(Clock())) 31 val en = IO(Input(Bool())) 32 val rIdx = IO(Input(UInt(DataBits.W))) 33 val rdata = IO(Output(UInt(DataBits.W))) 34 val wIdx = IO(Input(UInt(DataBits.W))) 35 val wdata = IO(Input(UInt(DataBits.W))) 36 val wmask = IO(Input(UInt(DataBits.W))) 37 val wen = IO(Input(Bool())) 38} 39 40class AXI4RAM 41( 42 address: Seq[AddressSet], 43 memByte: Long, 44 useBlackBox: Boolean = false, 45 executable: Boolean = true, 46 beatBytes: Int = 8, 47 burstLen: Int = 16, 48)(implicit p: Parameters) 49 extends AXI4SlaveModule(address, executable, beatBytes, burstLen) 50{ 51 override lazy val module = new AXI4SlaveModuleImp(this){ 52 53 val split = beatBytes / 8 54 val bankByte = memByte / split 55 val offsetBits = log2Up(memByte) 56 57 require(address.length >= 1) 58 val baseAddress = address(0).base 59 60 def index(addr: UInt) = ((addr - baseAddress.U)(offsetBits - 1, 0) >> log2Ceil(beatBytes)).asUInt() 61 62 def inRange(idx: UInt) = idx < (memByte / beatBytes).U 63 64 val wIdx = index(waddr) + writeBeatCnt 65 val rIdx = index(raddr) + readBeatCnt 66 val wen = in.w.fire() && inRange(wIdx) 67 require(beatBytes >= 8) 68 69 val rdata = if (useBlackBox) { 70 val mems = (0 until split).map {_ => Module(new RAMHelper(bankByte))} 71 mems.zipWithIndex map { case (mem, i) => 72 mem.clk := clock 73 mem.en := !reset.asBool() && ((state === s_rdata) || (state === s_wdata)) 74 mem.rIdx := (rIdx << log2Up(split)) + i.U 75 mem.wIdx := (wIdx << log2Up(split)) + i.U 76 mem.wdata := in.w.bits.data((i + 1) * 64 - 1, i * 64) 77 mem.wmask := MaskExpand(in.w.bits.strb((i + 1) * 8 - 1, i * 8)) 78 mem.wen := wen 79 } 80 val rdata = mems.map {mem => mem.rdata} 81 Cat(rdata.reverse) 82 } else { 83 val mem = Mem(memByte / beatBytes, Vec(beatBytes, UInt(8.W))) 84 85 val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8 * (i + 1) - 1, 8 * i) } 86 when(wen) { 87 mem.write(wIdx, wdata, in.w.bits.strb.asBools()) 88 } 89 90 Cat(mem.read(rIdx).reverse) 91 } 92 in.r.bits.data := rdata 93 } 94} 95 96class AXI4RAMWrapper 97(snode: AXI4SlaveNode, memByte: Long, useBlackBox: Boolean = false) 98(implicit p: Parameters) 99 extends LazyModule { 100 101 val mnode = AXI4MasterNode(List(snode.in.head._2.master)) 102 103 val portParam = snode.portParams.head 104 val slaveParam = portParam.slaves.head 105 val burstLen = portParam.maxTransfer / portParam.beatBytes 106 val ram = LazyModule(new AXI4RAM( 107 slaveParam.address, memByte, useBlackBox, 108 slaveParam.executable, portParam.beatBytes, burstLen 109 )) 110 ram.node := mnode 111 112 val io_axi4 = InModuleBody{ mnode.makeIOs() } 113 114 lazy val module = new LazyModuleImp(this){} 115} 116