1/dts-v1/; 2 3/ { 4 compatible = "xlnx,zynqmp-zcu102-rev1.0\0xlnx,zynqmp-zcu102\0xlnx,zynqmp"; 5 #address-cells = <0x02>; 6 #size-cells = <0x02>; 7 model = "ZynqMP ZCU102 Rev1.0"; 8 9 cpus { 10 #address-cells = <0x01>; 11 #size-cells = <0x00>; 12 13 cpu@0 { 14 compatible = "arm,cortex-a53"; 15 device_type = "cpu"; 16 enable-method = "psci"; 17 operating-points-v2 = <0x01>; 18 reg = <0x00>; 19 cpu-idle-states = <0x02>; 20 clocks = <0x03 0x0a>; 21 phandle = <0x3f>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 enable-method = "psci"; 28 reg = <0x01>; 29 operating-points-v2 = <0x01>; 30 cpu-idle-states = <0x02>; 31 phandle = <0x40>; 32 }; 33 34 cpu@2 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x02>; 39 operating-points-v2 = <0x01>; 40 cpu-idle-states = <0x02>; 41 phandle = <0x41>; 42 }; 43 44 cpu@3 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 enable-method = "psci"; 48 reg = <0x03>; 49 operating-points-v2 = <0x01>; 50 cpu-idle-states = <0x02>; 51 phandle = <0x42>; 52 }; 53 54 idle-states { 55 entry-method = "psci"; 56 57 cpu-sleep-0 { 58 compatible = "arm,idle-state"; 59 arm,psci-suspend-param = <0x40000000>; 60 local-timer-stop; 61 entry-latency-us = <0x12c>; 62 exit-latency-us = <0x258>; 63 min-residency-us = <0x2710>; 64 phandle = <0x02>; 65 }; 66 }; 67 }; 68 69 cpu-opp-table { 70 compatible = "operating-points-v2"; 71 opp-shared; 72 phandle = <0x01>; 73 74 opp00 { 75 opp-hz = <0x00 0x47868bf4>; 76 opp-microvolt = <0xf4240>; 77 clock-latency-ns = <0x7a120>; 78 }; 79 80 opp01 { 81 opp-hz = <0x00 0x23c345fa>; 82 opp-microvolt = <0xf4240>; 83 clock-latency-ns = <0x7a120>; 84 }; 85 86 opp02 { 87 opp-hz = <0x00 0x17d783fc>; 88 opp-microvolt = <0xf4240>; 89 clock-latency-ns = <0x7a120>; 90 }; 91 92 opp03 { 93 opp-hz = <0x00 0x11e1a2fd>; 94 opp-microvolt = <0xf4240>; 95 clock-latency-ns = <0x7a120>; 96 }; 97 }; 98 99 zynqmp_ipi { 100 u-boot,dm-pre-reloc; 101 compatible = "xlnx,zynqmp-ipi-mailbox"; 102 interrupt-parent = <0x04>; 103 interrupts = <0x00 0x23 0x04>; 104 xlnx,ipi-id = <0x00>; 105 #address-cells = <0x02>; 106 #size-cells = <0x02>; 107 ranges; 108 phandle = <0x43>; 109 110 mailbox@ff990400 { 111 u-boot,dm-pre-reloc; 112 reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>; 113 reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region"; 114 #mbox-cells = <0x01>; 115 xlnx,ipi-id = <0x04>; 116 phandle = <0x05>; 117 }; 118 }; 119 120 dcc { 121 compatible = "arm,dcc"; 122 status = "okay"; 123 u-boot,dm-pre-reloc; 124 phandle = <0x44>; 125 }; 126 127 pmu { 128 compatible = "arm,armv8-pmuv3"; 129 interrupt-parent = <0x04>; 130 interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>; 131 }; 132 133 psci { 134 compatible = "arm,psci-0.2"; 135 method = "smc"; 136 }; 137 138 firmware { 139 140 zynqmp-firmware { 141 compatible = "xlnx,zynqmp-firmware"; 142 #power-domain-cells = <0x01>; 143 method = "smc"; 144 u-boot,dm-pre-reloc; 145 phandle = <0x0c>; 146 147 zynqmp-power { 148 u-boot,dm-pre-reloc; 149 compatible = "xlnx,zynqmp-power"; 150 interrupt-parent = <0x04>; 151 interrupts = <0x00 0x23 0x04>; 152 mboxes = <0x05 0x00 0x05 0x01>; 153 mbox-names = "tx\0rx"; 154 phandle = <0x45>; 155 }; 156 157 nvmem_firmware { 158 compatible = "xlnx,zynqmp-nvmem-fw"; 159 #address-cells = <0x01>; 160 #size-cells = <0x01>; 161 162 soc_revision@0 { 163 reg = <0x00 0x04>; 164 phandle = <0x1e>; 165 }; 166 167 efuse_dna@c { 168 reg = <0x0c 0x0c>; 169 phandle = <0x46>; 170 }; 171 172 efuse_usr0@20 { 173 reg = <0x20 0x04>; 174 phandle = <0x47>; 175 }; 176 177 efuse_usr1@24 { 178 reg = <0x24 0x04>; 179 phandle = <0x48>; 180 }; 181 182 efuse_usr2@28 { 183 reg = <0x28 0x04>; 184 phandle = <0x49>; 185 }; 186 187 efuse_usr3@2c { 188 reg = <0x2c 0x04>; 189 phandle = <0x4a>; 190 }; 191 192 efuse_usr4@30 { 193 reg = <0x30 0x04>; 194 phandle = <0x4b>; 195 }; 196 197 efuse_usr5@34 { 198 reg = <0x34 0x04>; 199 phandle = <0x4c>; 200 }; 201 202 efuse_usr6@38 { 203 reg = <0x38 0x04>; 204 phandle = <0x4d>; 205 }; 206 207 efuse_usr7@3c { 208 reg = <0x3c 0x04>; 209 phandle = <0x4e>; 210 }; 211 212 efuse_miscusr@40 { 213 reg = <0x40 0x04>; 214 phandle = <0x4f>; 215 }; 216 217 efuse_chash@50 { 218 reg = <0x50 0x04>; 219 phandle = <0x50>; 220 }; 221 222 efuse_pufmisc@54 { 223 reg = <0x54 0x04>; 224 phandle = <0x51>; 225 }; 226 227 efuse_sec@58 { 228 reg = <0x58 0x04>; 229 phandle = <0x52>; 230 }; 231 232 efuse_spkid@5c { 233 reg = <0x5c 0x04>; 234 phandle = <0x53>; 235 }; 236 237 efuse_ppk0hash@a0 { 238 reg = <0xa0 0x30>; 239 phandle = <0x54>; 240 }; 241 242 efuse_ppk1hash@d0 { 243 reg = <0xd0 0x30>; 244 phandle = <0x55>; 245 }; 246 }; 247 248 pcap { 249 compatible = "xlnx,zynqmp-pcap-fpga"; 250 clock-names = "ref_clk"; 251 clocks = <0x03 0x29>; 252 phandle = <0x0b>; 253 }; 254 255 zynqmp-aes { 256 compatible = "xlnx,zynqmp-aes"; 257 phandle = <0x56>; 258 }; 259 260 reset-controller { 261 compatible = "xlnx,zynqmp-reset"; 262 #reset-cells = <0x01>; 263 phandle = <0x1c>; 264 }; 265 266 pinctrl { 267 compatible = "xlnx,zynqmp-pinctrl"; 268 status = "okay"; 269 phandle = <0x57>; 270 271 i2c0-default { 272 phandle = <0x12>; 273 274 mux { 275 groups = "i2c0_3_grp"; 276 function = "i2c0"; 277 }; 278 279 conf { 280 groups = "i2c0_3_grp"; 281 bias-pull-up; 282 slew-rate = <0x01>; 283 power-source = <0x01>; 284 }; 285 }; 286 287 i2c0-gpio { 288 phandle = <0x13>; 289 290 mux { 291 groups = "gpio0_14_grp\0gpio0_15_grp"; 292 function = "gpio0"; 293 }; 294 295 conf { 296 groups = "gpio0_14_grp\0gpio0_15_grp"; 297 slew-rate = <0x01>; 298 power-source = <0x01>; 299 }; 300 }; 301 302 i2c1-default { 303 phandle = <0x15>; 304 305 mux { 306 groups = "i2c1_4_grp"; 307 function = "i2c1"; 308 }; 309 310 conf { 311 groups = "i2c1_4_grp"; 312 bias-pull-up; 313 slew-rate = <0x01>; 314 power-source = <0x01>; 315 }; 316 }; 317 318 i2c1-gpio { 319 phandle = <0x16>; 320 321 mux { 322 groups = "gpio0_16_grp\0gpio0_17_grp"; 323 function = "gpio0"; 324 }; 325 326 conf { 327 groups = "gpio0_16_grp\0gpio0_17_grp"; 328 slew-rate = <0x01>; 329 power-source = <0x01>; 330 }; 331 }; 332 333 uart0-default { 334 phandle = <0x21>; 335 336 mux { 337 groups = "uart0_4_grp"; 338 function = "uart0"; 339 }; 340 341 conf { 342 groups = "uart0_4_grp"; 343 slew-rate = <0x01>; 344 power-source = <0x01>; 345 }; 346 347 conf-rx { 348 pins = "MIO18"; 349 bias-high-impedance; 350 }; 351 352 conf-tx { 353 pins = "MIO19"; 354 bias-disable; 355 }; 356 }; 357 358 uart1-default { 359 phandle = <0x22>; 360 361 mux { 362 groups = "uart1_5_grp"; 363 function = "uart1"; 364 }; 365 366 conf { 367 groups = "uart1_5_grp"; 368 slew-rate = <0x01>; 369 power-source = <0x01>; 370 }; 371 372 conf-rx { 373 pins = "MIO21"; 374 bias-high-impedance; 375 }; 376 377 conf-tx { 378 pins = "MIO20"; 379 bias-disable; 380 }; 381 }; 382 383 usb0-default { 384 phandle = <0x24>; 385 386 mux { 387 groups = "usb0_0_grp"; 388 function = "usb0"; 389 }; 390 391 conf { 392 groups = "usb0_0_grp"; 393 slew-rate = <0x01>; 394 power-source = <0x01>; 395 }; 396 397 conf-rx { 398 pins = "MIO52\0MIO53\0MIO55"; 399 bias-high-impedance; 400 }; 401 402 conf-tx { 403 pins = "MIO54\0MIO56\0MIO57\0MIO58\0MIO59\0MIO60\0MIO61\0MIO62\0MIO63"; 404 bias-disable; 405 }; 406 }; 407 408 gem3-default { 409 phandle = <0x10>; 410 411 mux { 412 function = "ethernet3"; 413 groups = "ethernet3_0_grp"; 414 }; 415 416 conf { 417 groups = "ethernet3_0_grp"; 418 slew-rate = <0x01>; 419 power-source = <0x01>; 420 }; 421 422 conf-rx { 423 pins = "MIO70\0MIO71\0MIO72\0MIO73\0MIO74\0MIO75"; 424 bias-high-impedance; 425 low-power-disable; 426 }; 427 428 conf-tx { 429 pins = "MIO64\0MIO65\0MIO66\0MIO67\0MIO68\0MIO69"; 430 bias-disable; 431 low-power-enable; 432 }; 433 434 mux-mdio { 435 function = "mdio3"; 436 groups = "mdio3_0_grp"; 437 }; 438 439 conf-mdio { 440 groups = "mdio3_0_grp"; 441 slew-rate = <0x01>; 442 power-source = <0x01>; 443 bias-disable; 444 }; 445 }; 446 447 can1-default { 448 phandle = <0x0d>; 449 450 mux { 451 function = "can1"; 452 groups = "can1_6_grp"; 453 }; 454 455 conf { 456 groups = "can1_6_grp"; 457 slew-rate = <0x01>; 458 power-source = <0x01>; 459 }; 460 461 conf-rx { 462 pins = "MIO25"; 463 bias-high-impedance; 464 }; 465 466 conf-tx { 467 pins = "MIO24"; 468 bias-disable; 469 }; 470 }; 471 472 sdhci1-default { 473 phandle = <0x1f>; 474 475 mux { 476 groups = "sdio1_0_grp"; 477 function = "sdio1"; 478 }; 479 480 conf { 481 groups = "sdio1_0_grp"; 482 slew-rate = <0x01>; 483 power-source = <0x01>; 484 bias-disable; 485 }; 486 487 mux-cd { 488 groups = "sdio1_cd_0_grp"; 489 function = "sdio1_cd"; 490 }; 491 492 conf-cd { 493 groups = "sdio1_cd_0_grp"; 494 bias-high-impedance; 495 bias-pull-up; 496 slew-rate = <0x01>; 497 power-source = <0x01>; 498 }; 499 500 mux-wp { 501 groups = "sdio1_wp_0_grp"; 502 function = "sdio1_wp"; 503 }; 504 505 conf-wp { 506 groups = "sdio1_wp_0_grp"; 507 bias-high-impedance; 508 bias-pull-up; 509 slew-rate = <0x01>; 510 power-source = <0x01>; 511 }; 512 }; 513 514 gpio-default { 515 phandle = <0x11>; 516 517 mux-sw { 518 function = "gpio0"; 519 groups = "gpio0_22_grp\0gpio0_23_grp"; 520 }; 521 522 conf-sw { 523 groups = "gpio0_22_grp\0gpio0_23_grp"; 524 slew-rate = <0x01>; 525 power-source = <0x01>; 526 }; 527 528 mux-msp { 529 function = "gpio0"; 530 groups = "gpio0_13_grp\0gpio0_38_grp"; 531 }; 532 533 conf-msp { 534 groups = "gpio0_13_grp\0gpio0_38_grp"; 535 slew-rate = <0x01>; 536 power-source = <0x01>; 537 }; 538 539 conf-pull-up { 540 pins = "MIO22\0MIO23"; 541 bias-pull-up; 542 }; 543 544 conf-pull-none { 545 pins = "MIO13\0MIO38"; 546 bias-disable; 547 }; 548 }; 549 }; 550 551 sha384 { 552 compatible = "xlnx,zynqmp-keccak-384"; 553 phandle = <0x58>; 554 }; 555 556 zynqmp-rsa { 557 compatible = "xlnx,zynqmp-rsa"; 558 phandle = <0x59>; 559 }; 560 561 gpio { 562 compatible = "xlnx,zynqmp-gpio-modepin"; 563 gpio-controller; 564 #gpio-cells = <0x02>; 565 phandle = <0x23>; 566 }; 567 568 clock-controller { 569 u-boot,dm-pre-reloc; 570 #clock-cells = <0x01>; 571 compatible = "xlnx,zynqmp-clk"; 572 clocks = <0x06 0x07 0x08 0x09 0x0a>; 573 clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk"; 574 phandle = <0x03>; 575 }; 576 }; 577 }; 578 579 timer { 580 compatible = "arm,armv8-timer"; 581 interrupt-parent = <0x04>; 582 interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; 583 }; 584 585 edac { 586 compatible = "arm,cortex-a53-edac"; 587 }; 588 589 fpga-full { 590 compatible = "fpga-region"; 591 fpga-mgr = <0x0b>; 592 #address-cells = <0x02>; 593 #size-cells = <0x02>; 594 ranges; 595 phandle = <0x5a>; 596 }; 597 598 smmu@fd800000 { 599 compatible = "arm,mmu-500"; 600 reg = <0x00 0xfd800000 0x00 0x20000>; 601 #iommu-cells = <0x01>; 602 status = "disabled"; 603 #global-interrupts = <0x01>; 604 interrupt-parent = <0x04>; 605 interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>; 606 phandle = <0x0e>; 607 }; 608 609 axi { 610 compatible = "simple-bus"; 611 u-boot,dm-pre-reloc; 612 #address-cells = <0x02>; 613 #size-cells = <0x02>; 614 ranges; 615 phandle = <0x5b>; 616 617 can@ff060000 { 618 compatible = "xlnx,zynq-can-1.0"; 619 status = "disabled"; 620 clock-names = "can_clk\0pclk"; 621 reg = <0x00 0xff060000 0x00 0x1000>; 622 interrupts = <0x00 0x17 0x04>; 623 interrupt-parent = <0x04>; 624 tx-fifo-depth = <0x40>; 625 rx-fifo-depth = <0x40>; 626 power-domains = <0x0c 0x2f>; 627 clocks = <0x03 0x3f 0x03 0x1f>; 628 phandle = <0x5c>; 629 }; 630 631 can@ff070000 { 632 compatible = "xlnx,zynq-can-1.0"; 633 status = "okay"; 634 clock-names = "can_clk\0pclk"; 635 reg = <0x00 0xff070000 0x00 0x1000>; 636 interrupts = <0x00 0x18 0x04>; 637 interrupt-parent = <0x04>; 638 tx-fifo-depth = <0x40>; 639 rx-fifo-depth = <0x40>; 640 power-domains = <0x0c 0x30>; 641 clocks = <0x03 0x40 0x03 0x1f>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <0x0d>; 644 phandle = <0x5d>; 645 }; 646 647 cci@fd6e0000 { 648 compatible = "arm,cci-400"; 649 status = "disabled"; 650 reg = <0x00 0xfd6e0000 0x00 0x9000>; 651 ranges = <0x00 0x00 0xfd6e0000 0x10000>; 652 #address-cells = <0x01>; 653 #size-cells = <0x01>; 654 phandle = <0x5e>; 655 656 pmu@9000 { 657 compatible = "arm,cci-400-pmu,r1"; 658 reg = <0x9000 0x5000>; 659 interrupt-parent = <0x04>; 660 interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>; 661 }; 662 }; 663 664 dma@fd500000 { 665 status = "okay"; 666 compatible = "xlnx,zynqmp-dma-1.0"; 667 reg = <0x00 0xfd500000 0x00 0x1000>; 668 interrupt-parent = <0x04>; 669 interrupts = <0x00 0x7c 0x04>; 670 clock-names = "clk_main\0clk_apb"; 671 xlnx,bus-width = <0x80>; 672 #stream-id-cells = <0x01>; 673 iommus = <0x0e 0x14e8>; 674 power-domains = <0x0c 0x2a>; 675 clocks = <0x03 0x13 0x03 0x1f>; 676 phandle = <0x5f>; 677 }; 678 679 dma@fd510000 { 680 status = "okay"; 681 compatible = "xlnx,zynqmp-dma-1.0"; 682 reg = <0x00 0xfd510000 0x00 0x1000>; 683 interrupt-parent = <0x04>; 684 interrupts = <0x00 0x7d 0x04>; 685 clock-names = "clk_main\0clk_apb"; 686 xlnx,bus-width = <0x80>; 687 #stream-id-cells = <0x01>; 688 iommus = <0x0e 0x14e9>; 689 power-domains = <0x0c 0x2a>; 690 clocks = <0x03 0x13 0x03 0x1f>; 691 phandle = <0x60>; 692 }; 693 694 dma@fd520000 { 695 status = "okay"; 696 compatible = "xlnx,zynqmp-dma-1.0"; 697 reg = <0x00 0xfd520000 0x00 0x1000>; 698 interrupt-parent = <0x04>; 699 interrupts = <0x00 0x7e 0x04>; 700 clock-names = "clk_main\0clk_apb"; 701 xlnx,bus-width = <0x80>; 702 #stream-id-cells = <0x01>; 703 iommus = <0x0e 0x14ea>; 704 power-domains = <0x0c 0x2a>; 705 clocks = <0x03 0x13 0x03 0x1f>; 706 phandle = <0x61>; 707 }; 708 709 dma@fd530000 { 710 status = "okay"; 711 compatible = "xlnx,zynqmp-dma-1.0"; 712 reg = <0x00 0xfd530000 0x00 0x1000>; 713 interrupt-parent = <0x04>; 714 interrupts = <0x00 0x7f 0x04>; 715 clock-names = "clk_main\0clk_apb"; 716 xlnx,bus-width = <0x80>; 717 #stream-id-cells = <0x01>; 718 iommus = <0x0e 0x14eb>; 719 power-domains = <0x0c 0x2a>; 720 clocks = <0x03 0x13 0x03 0x1f>; 721 phandle = <0x62>; 722 }; 723 724 dma@fd540000 { 725 status = "okay"; 726 compatible = "xlnx,zynqmp-dma-1.0"; 727 reg = <0x00 0xfd540000 0x00 0x1000>; 728 interrupt-parent = <0x04>; 729 interrupts = <0x00 0x80 0x04>; 730 clock-names = "clk_main\0clk_apb"; 731 xlnx,bus-width = <0x80>; 732 #stream-id-cells = <0x01>; 733 iommus = <0x0e 0x14ec>; 734 power-domains = <0x0c 0x2a>; 735 clocks = <0x03 0x13 0x03 0x1f>; 736 phandle = <0x63>; 737 }; 738 739 dma@fd550000 { 740 status = "okay"; 741 compatible = "xlnx,zynqmp-dma-1.0"; 742 reg = <0x00 0xfd550000 0x00 0x1000>; 743 interrupt-parent = <0x04>; 744 interrupts = <0x00 0x81 0x04>; 745 clock-names = "clk_main\0clk_apb"; 746 xlnx,bus-width = <0x80>; 747 #stream-id-cells = <0x01>; 748 iommus = <0x0e 0x14ed>; 749 power-domains = <0x0c 0x2a>; 750 clocks = <0x03 0x13 0x03 0x1f>; 751 phandle = <0x64>; 752 }; 753 754 dma@fd560000 { 755 status = "okay"; 756 compatible = "xlnx,zynqmp-dma-1.0"; 757 reg = <0x00 0xfd560000 0x00 0x1000>; 758 interrupt-parent = <0x04>; 759 interrupts = <0x00 0x82 0x04>; 760 clock-names = "clk_main\0clk_apb"; 761 xlnx,bus-width = <0x80>; 762 #stream-id-cells = <0x01>; 763 iommus = <0x0e 0x14ee>; 764 power-domains = <0x0c 0x2a>; 765 clocks = <0x03 0x13 0x03 0x1f>; 766 phandle = <0x65>; 767 }; 768 769 dma@fd570000 { 770 status = "okay"; 771 compatible = "xlnx,zynqmp-dma-1.0"; 772 reg = <0x00 0xfd570000 0x00 0x1000>; 773 interrupt-parent = <0x04>; 774 interrupts = <0x00 0x83 0x04>; 775 clock-names = "clk_main\0clk_apb"; 776 xlnx,bus-width = <0x80>; 777 #stream-id-cells = <0x01>; 778 iommus = <0x0e 0x14ef>; 779 power-domains = <0x0c 0x2a>; 780 clocks = <0x03 0x13 0x03 0x1f>; 781 phandle = <0x66>; 782 }; 783 784 interrupt-controller@f9010000 { 785 compatible = "arm,gic-400"; 786 #interrupt-cells = <0x03>; 787 reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>; 788 interrupt-controller; 789 interrupt-parent = <0x04>; 790 interrupts = <0x01 0x09 0xf04>; 791 phandle = <0x04>; 792 }; 793 794 gpu@fd4b0000 { 795 status = "okay"; 796 compatible = "arm,mali-400\0arm,mali-utgard"; 797 reg = <0x00 0xfd4b0000 0x00 0x10000>; 798 interrupt-parent = <0x04>; 799 interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>; 800 interrupt-names = "IRQGP\0IRQGPMMU\0IRQPP0\0IRQPPMMU0\0IRQPP1\0IRQPPMMU1"; 801 clock-names = "gpu\0gpu_pp0\0gpu_pp1"; 802 power-domains = <0x0c 0x3a>; 803 clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>; 804 phandle = <0x67>; 805 }; 806 807 dma@ffa80000 { 808 status = "disabled"; 809 compatible = "xlnx,zynqmp-dma-1.0"; 810 reg = <0x00 0xffa80000 0x00 0x1000>; 811 interrupt-parent = <0x04>; 812 interrupts = <0x00 0x4d 0x04>; 813 clock-names = "clk_main\0clk_apb"; 814 xlnx,bus-width = <0x40>; 815 #stream-id-cells = <0x01>; 816 power-domains = <0x0c 0x2b>; 817 clocks = <0x03 0x44 0x03 0x1f>; 818 phandle = <0x68>; 819 }; 820 821 dma@ffa90000 { 822 status = "disabled"; 823 compatible = "xlnx,zynqmp-dma-1.0"; 824 reg = <0x00 0xffa90000 0x00 0x1000>; 825 interrupt-parent = <0x04>; 826 interrupts = <0x00 0x4e 0x04>; 827 clock-names = "clk_main\0clk_apb"; 828 xlnx,bus-width = <0x40>; 829 #stream-id-cells = <0x01>; 830 power-domains = <0x0c 0x2b>; 831 clocks = <0x03 0x44 0x03 0x1f>; 832 phandle = <0x69>; 833 }; 834 835 dma@ffaa0000 { 836 status = "disabled"; 837 compatible = "xlnx,zynqmp-dma-1.0"; 838 reg = <0x00 0xffaa0000 0x00 0x1000>; 839 interrupt-parent = <0x04>; 840 interrupts = <0x00 0x4f 0x04>; 841 clock-names = "clk_main\0clk_apb"; 842 xlnx,bus-width = <0x40>; 843 #stream-id-cells = <0x01>; 844 power-domains = <0x0c 0x2b>; 845 clocks = <0x03 0x44 0x03 0x1f>; 846 phandle = <0x6a>; 847 }; 848 849 dma@ffab0000 { 850 status = "disabled"; 851 compatible = "xlnx,zynqmp-dma-1.0"; 852 reg = <0x00 0xffab0000 0x00 0x1000>; 853 interrupt-parent = <0x04>; 854 interrupts = <0x00 0x50 0x04>; 855 clock-names = "clk_main\0clk_apb"; 856 xlnx,bus-width = <0x40>; 857 #stream-id-cells = <0x01>; 858 power-domains = <0x0c 0x2b>; 859 clocks = <0x03 0x44 0x03 0x1f>; 860 phandle = <0x6b>; 861 }; 862 863 dma@ffac0000 { 864 status = "disabled"; 865 compatible = "xlnx,zynqmp-dma-1.0"; 866 reg = <0x00 0xffac0000 0x00 0x1000>; 867 interrupt-parent = <0x04>; 868 interrupts = <0x00 0x51 0x04>; 869 clock-names = "clk_main\0clk_apb"; 870 xlnx,bus-width = <0x40>; 871 #stream-id-cells = <0x01>; 872 power-domains = <0x0c 0x2b>; 873 clocks = <0x03 0x44 0x03 0x1f>; 874 phandle = <0x6c>; 875 }; 876 877 dma@ffad0000 { 878 status = "disabled"; 879 compatible = "xlnx,zynqmp-dma-1.0"; 880 reg = <0x00 0xffad0000 0x00 0x1000>; 881 interrupt-parent = <0x04>; 882 interrupts = <0x00 0x52 0x04>; 883 clock-names = "clk_main\0clk_apb"; 884 xlnx,bus-width = <0x40>; 885 #stream-id-cells = <0x01>; 886 power-domains = <0x0c 0x2b>; 887 clocks = <0x03 0x44 0x03 0x1f>; 888 phandle = <0x6d>; 889 }; 890 891 dma@ffae0000 { 892 status = "disabled"; 893 compatible = "xlnx,zynqmp-dma-1.0"; 894 reg = <0x00 0xffae0000 0x00 0x1000>; 895 interrupt-parent = <0x04>; 896 interrupts = <0x00 0x53 0x04>; 897 clock-names = "clk_main\0clk_apb"; 898 xlnx,bus-width = <0x40>; 899 #stream-id-cells = <0x01>; 900 power-domains = <0x0c 0x2b>; 901 clocks = <0x03 0x44 0x03 0x1f>; 902 phandle = <0x6e>; 903 }; 904 905 dma@ffaf0000 { 906 status = "disabled"; 907 compatible = "xlnx,zynqmp-dma-1.0"; 908 reg = <0x00 0xffaf0000 0x00 0x1000>; 909 interrupt-parent = <0x04>; 910 interrupts = <0x00 0x54 0x04>; 911 clock-names = "clk_main\0clk_apb"; 912 xlnx,bus-width = <0x40>; 913 #stream-id-cells = <0x01>; 914 power-domains = <0x0c 0x2b>; 915 clocks = <0x03 0x44 0x03 0x1f>; 916 phandle = <0x6f>; 917 }; 918 919 memory-controller@fd070000 { 920 compatible = "xlnx,zynqmp-ddrc-2.40a"; 921 reg = <0x00 0xfd070000 0x00 0x30000>; 922 interrupt-parent = <0x04>; 923 interrupts = <0x00 0x70 0x04>; 924 phandle = <0x70>; 925 }; 926 927 nand-controller@ff100000 { 928 compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10"; 929 status = "disabled"; 930 reg = <0x00 0xff100000 0x00 0x1000>; 931 clock-names = "controller\0bus"; 932 interrupt-parent = <0x04>; 933 interrupts = <0x00 0x0e 0x04>; 934 #address-cells = <0x01>; 935 #size-cells = <0x00>; 936 #stream-id-cells = <0x01>; 937 iommus = <0x0e 0x872>; 938 power-domains = <0x0c 0x2c>; 939 clocks = <0x03 0x3c 0x03 0x1f>; 940 phandle = <0x71>; 941 }; 942 943 ethernet@ff0b0000 { 944 compatible = "cdns,zynqmp-gem\0cdns,gem"; 945 status = "disabled"; 946 interrupt-parent = <0x04>; 947 interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>; 948 reg = <0x00 0xff0b0000 0x00 0x1000>; 949 clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; 950 #address-cells = <0x01>; 951 #size-cells = <0x00>; 952 #stream-id-cells = <0x01>; 953 iommus = <0x0e 0x874>; 954 power-domains = <0x0c 0x1d>; 955 clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>; 956 phandle = <0x72>; 957 }; 958 959 ethernet@ff0c0000 { 960 compatible = "cdns,zynqmp-gem\0cdns,gem"; 961 status = "disabled"; 962 interrupt-parent = <0x04>; 963 interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>; 964 reg = <0x00 0xff0c0000 0x00 0x1000>; 965 clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; 966 #address-cells = <0x01>; 967 #size-cells = <0x00>; 968 #stream-id-cells = <0x01>; 969 iommus = <0x0e 0x875>; 970 power-domains = <0x0c 0x1e>; 971 clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>; 972 phandle = <0x73>; 973 }; 974 975 ethernet@ff0d0000 { 976 compatible = "cdns,zynqmp-gem\0cdns,gem"; 977 status = "disabled"; 978 interrupt-parent = <0x04>; 979 interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>; 980 reg = <0x00 0xff0d0000 0x00 0x1000>; 981 clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; 982 #address-cells = <0x01>; 983 #size-cells = <0x00>; 984 #stream-id-cells = <0x01>; 985 iommus = <0x0e 0x876>; 986 power-domains = <0x0c 0x1f>; 987 clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>; 988 phandle = <0x74>; 989 }; 990 991 ethernet@ff0e0000 { 992 compatible = "cdns,zynqmp-gem\0cdns,gem"; 993 status = "okay"; 994 interrupt-parent = <0x04>; 995 interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>; 996 reg = <0x00 0xff0e0000 0x00 0x1000>; 997 clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; 998 #address-cells = <0x01>; 999 #size-cells = <0x00>; 1000 #stream-id-cells = <0x01>; 1001 iommus = <0x0e 0x877>; 1002 power-domains = <0x0c 0x20>; 1003 clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>; 1004 phy-handle = <0x0f>; 1005 phy-mode = "rgmii-id"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <0x10>; 1008 phandle = <0x75>; 1009 1010 ethernet-phy@c { 1011 reg = <0x0c>; 1012 ti,rx-internal-delay = <0x08>; 1013 ti,tx-internal-delay = <0x0a>; 1014 ti,fifo-depth = <0x01>; 1015 ti,dp83867-rxctrl-strap-quirk; 1016 phandle = <0x0f>; 1017 }; 1018 }; 1019 1020 gpio@ff0a0000 { 1021 compatible = "xlnx,zynqmp-gpio-1.0"; 1022 status = "okay"; 1023 #gpio-cells = <0x02>; 1024 gpio-controller; 1025 interrupt-parent = <0x04>; 1026 interrupts = <0x00 0x10 0x04>; 1027 interrupt-controller; 1028 #interrupt-cells = <0x02>; 1029 reg = <0x00 0xff0a0000 0x00 0x1000>; 1030 power-domains = <0x0c 0x2e>; 1031 clocks = <0x03 0x1f>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <0x11>; 1034 phandle = <0x14>; 1035 }; 1036 1037 i2c@ff020000 { 1038 compatible = "cdns,i2c-r1p14"; 1039 status = "okay"; 1040 interrupt-parent = <0x04>; 1041 interrupts = <0x00 0x11 0x04>; 1042 reg = <0x00 0xff020000 0x00 0x1000>; 1043 #address-cells = <0x01>; 1044 #size-cells = <0x00>; 1045 power-domains = <0x0c 0x25>; 1046 clocks = <0x03 0x3d>; 1047 clock-frequency = <0x61a80>; 1048 pinctrl-names = "default\0gpio"; 1049 pinctrl-0 = <0x12>; 1050 pinctrl-1 = <0x13>; 1051 scl-gpios = <0x14 0x0e 0x00>; 1052 sda-gpios = <0x14 0x0f 0x00>; 1053 phandle = <0x76>; 1054 1055 gpio@20 { 1056 compatible = "ti,tca6416"; 1057 reg = <0x20>; 1058 gpio-controller; 1059 #gpio-cells = <0x02>; 1060 gpio-line-names = "PS_GTR_LAN_SEL0\0PS_GTR_LAN_SEL1\0PS_GTR_LAN_SEL2\0PS_GTR_LAN_SEL3\0PCI_CLK_DIR_SEL\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0\0\0\0\0\0\0\0\0"; 1061 phandle = <0x77>; 1062 1063 gtr-sel0-hog { 1064 gpio-hog; 1065 gpios = <0x00 0x00>; 1066 output-low; 1067 line-name = "sel0"; 1068 }; 1069 1070 gtr-sel1-hog { 1071 gpio-hog; 1072 gpios = <0x01 0x00>; 1073 output-high; 1074 line-name = "sel1"; 1075 }; 1076 1077 gtr-sel2-hog { 1078 gpio-hog; 1079 gpios = <0x02 0x00>; 1080 output-high; 1081 line-name = "sel2"; 1082 }; 1083 1084 gtr-sel3-hog { 1085 gpio-hog; 1086 gpios = <0x03 0x00>; 1087 output-high; 1088 line-name = "sel3"; 1089 }; 1090 }; 1091 1092 gpio@21 { 1093 compatible = "ti,tca6416"; 1094 reg = <0x21>; 1095 gpio-controller; 1096 #gpio-cells = <0x02>; 1097 gpio-line-names = "VCCPSPLL_EN\0MGTRAVCC_EN\0MGTRAVTT_EN\0VCCPSDDRPLL_EN\0MIO26_PMU_INPUT_LS\0PL_PMBUS_ALERT\0PS_PMBUS_ALERT\0MAXIM_PMBUS_ALERT\0PL_DDR4_VTERM_EN\0PL_DDR4_VPP_2V5_EN\0PS_DIMM_VDDQ_TO_PSVCCO_ON\0PS_DIMM_SUSPEND_EN\0PS_DDR4_VTERM_EN\0PS_DDR4_VPP_2V5_EN\0\0"; 1098 phandle = <0x78>; 1099 }; 1100 1101 i2c-mux@75 { 1102 compatible = "nxp,pca9544"; 1103 #address-cells = <0x01>; 1104 #size-cells = <0x00>; 1105 reg = <0x75>; 1106 1107 i2c@0 { 1108 #address-cells = <0x01>; 1109 #size-cells = <0x00>; 1110 reg = <0x00>; 1111 1112 ina226@40 { 1113 compatible = "ti,ina226"; 1114 #io-channel-cells = <0x01>; 1115 label = "ina226-u76"; 1116 reg = <0x40>; 1117 shunt-resistor = <0x1388>; 1118 phandle = <0x2a>; 1119 }; 1120 1121 ina226@41 { 1122 compatible = "ti,ina226"; 1123 #io-channel-cells = <0x01>; 1124 label = "ina226-u77"; 1125 reg = <0x41>; 1126 shunt-resistor = <0x1388>; 1127 phandle = <0x2b>; 1128 }; 1129 1130 ina226@42 { 1131 compatible = "ti,ina226"; 1132 #io-channel-cells = <0x01>; 1133 label = "ina226-u78"; 1134 reg = <0x42>; 1135 shunt-resistor = <0x1388>; 1136 phandle = <0x2c>; 1137 }; 1138 1139 ina226@43 { 1140 compatible = "ti,ina226"; 1141 #io-channel-cells = <0x01>; 1142 label = "ina226-u87"; 1143 reg = <0x43>; 1144 shunt-resistor = <0x1388>; 1145 phandle = <0x2d>; 1146 }; 1147 1148 ina226@44 { 1149 compatible = "ti,ina226"; 1150 #io-channel-cells = <0x01>; 1151 label = "ina226-u85"; 1152 reg = <0x44>; 1153 shunt-resistor = <0x1388>; 1154 phandle = <0x2e>; 1155 }; 1156 1157 ina226@45 { 1158 compatible = "ti,ina226"; 1159 #io-channel-cells = <0x01>; 1160 label = "ina226-u86"; 1161 reg = <0x45>; 1162 shunt-resistor = <0x1388>; 1163 phandle = <0x2f>; 1164 }; 1165 1166 ina226@46 { 1167 compatible = "ti,ina226"; 1168 #io-channel-cells = <0x01>; 1169 label = "ina226-u93"; 1170 reg = <0x46>; 1171 shunt-resistor = <0x1388>; 1172 phandle = <0x30>; 1173 }; 1174 1175 ina226@47 { 1176 compatible = "ti,ina226"; 1177 #io-channel-cells = <0x01>; 1178 label = "ina226-u88"; 1179 reg = <0x47>; 1180 shunt-resistor = <0x1388>; 1181 phandle = <0x31>; 1182 }; 1183 1184 ina226@4a { 1185 compatible = "ti,ina226"; 1186 #io-channel-cells = <0x01>; 1187 label = "ina226-u15"; 1188 reg = <0x4a>; 1189 shunt-resistor = <0x1388>; 1190 phandle = <0x32>; 1191 }; 1192 1193 ina226@4b { 1194 compatible = "ti,ina226"; 1195 #io-channel-cells = <0x01>; 1196 label = "ina226-u92"; 1197 reg = <0x4b>; 1198 shunt-resistor = <0x1388>; 1199 phandle = <0x33>; 1200 }; 1201 }; 1202 1203 i2c@1 { 1204 #address-cells = <0x01>; 1205 #size-cells = <0x00>; 1206 reg = <0x01>; 1207 1208 ina226@40 { 1209 compatible = "ti,ina226"; 1210 #io-channel-cells = <0x01>; 1211 label = "ina226-u79"; 1212 reg = <0x40>; 1213 shunt-resistor = <0x7d0>; 1214 phandle = <0x34>; 1215 }; 1216 1217 ina226@41 { 1218 compatible = "ti,ina226"; 1219 #io-channel-cells = <0x01>; 1220 label = "ina226-u81"; 1221 reg = <0x41>; 1222 shunt-resistor = <0x1388>; 1223 phandle = <0x35>; 1224 }; 1225 1226 ina226@42 { 1227 compatible = "ti,ina226"; 1228 #io-channel-cells = <0x01>; 1229 label = "ina226-u80"; 1230 reg = <0x42>; 1231 shunt-resistor = <0x1388>; 1232 phandle = <0x36>; 1233 }; 1234 1235 ina226@43 { 1236 compatible = "ti,ina226"; 1237 #io-channel-cells = <0x01>; 1238 label = "ina226-u84"; 1239 reg = <0x43>; 1240 shunt-resistor = <0x1388>; 1241 phandle = <0x37>; 1242 }; 1243 1244 ina226@44 { 1245 compatible = "ti,ina226"; 1246 #io-channel-cells = <0x01>; 1247 label = "ina226-u16"; 1248 reg = <0x44>; 1249 shunt-resistor = <0x1388>; 1250 phandle = <0x38>; 1251 }; 1252 1253 ina226@45 { 1254 compatible = "ti,ina226"; 1255 #io-channel-cells = <0x01>; 1256 label = "ina226-u65"; 1257 reg = <0x45>; 1258 shunt-resistor = <0x1388>; 1259 phandle = <0x39>; 1260 }; 1261 1262 ina226@46 { 1263 compatible = "ti,ina226"; 1264 #io-channel-cells = <0x01>; 1265 label = "ina226-u74"; 1266 reg = <0x46>; 1267 shunt-resistor = <0x1388>; 1268 phandle = <0x3a>; 1269 }; 1270 1271 ina226@47 { 1272 compatible = "ti,ina226"; 1273 #io-channel-cells = <0x01>; 1274 label = "ina226-u75"; 1275 reg = <0x47>; 1276 shunt-resistor = <0x1388>; 1277 phandle = <0x3b>; 1278 }; 1279 }; 1280 1281 i2c@2 { 1282 #address-cells = <0x01>; 1283 #size-cells = <0x00>; 1284 reg = <0x02>; 1285 1286 max15301@a { 1287 compatible = "maxim,max15301"; 1288 reg = <0x0a>; 1289 }; 1290 1291 max15303@b { 1292 compatible = "maxim,max15303"; 1293 reg = <0x0b>; 1294 }; 1295 1296 max15303@10 { 1297 compatible = "maxim,max15303"; 1298 reg = <0x10>; 1299 }; 1300 1301 max15301@13 { 1302 compatible = "maxim,max15301"; 1303 reg = <0x13>; 1304 }; 1305 1306 max15303@14 { 1307 compatible = "maxim,max15303"; 1308 reg = <0x14>; 1309 }; 1310 1311 max15303@15 { 1312 compatible = "maxim,max15303"; 1313 reg = <0x15>; 1314 }; 1315 1316 max15303@16 { 1317 compatible = "maxim,max15303"; 1318 reg = <0x16>; 1319 }; 1320 1321 max15303@17 { 1322 compatible = "maxim,max15303"; 1323 reg = <0x17>; 1324 }; 1325 1326 max15301@18 { 1327 compatible = "maxim,max15301"; 1328 reg = <0x18>; 1329 }; 1330 1331 max15303@1a { 1332 compatible = "maxim,max15303"; 1333 reg = <0x1a>; 1334 }; 1335 1336 max15303@1d { 1337 compatible = "maxim,max15303"; 1338 reg = <0x1d>; 1339 }; 1340 1341 max20751@72 { 1342 compatible = "maxim,max20751"; 1343 reg = <0x72>; 1344 }; 1345 1346 max20751@73 { 1347 compatible = "maxim,max20751"; 1348 reg = <0x73>; 1349 }; 1350 1351 max15303@1b { 1352 compatible = "maxim,max15303"; 1353 reg = <0x1b>; 1354 }; 1355 }; 1356 }; 1357 }; 1358 1359 i2c@ff030000 { 1360 compatible = "cdns,i2c-r1p14"; 1361 status = "okay"; 1362 interrupt-parent = <0x04>; 1363 interrupts = <0x00 0x12 0x04>; 1364 reg = <0x00 0xff030000 0x00 0x1000>; 1365 #address-cells = <0x01>; 1366 #size-cells = <0x00>; 1367 power-domains = <0x0c 0x26>; 1368 clocks = <0x03 0x3e>; 1369 clock-frequency = <0x61a80>; 1370 pinctrl-names = "default\0gpio"; 1371 pinctrl-0 = <0x15>; 1372 pinctrl-1 = <0x16>; 1373 scl-gpios = <0x14 0x10 0x00>; 1374 sda-gpios = <0x14 0x11 0x00>; 1375 phandle = <0x79>; 1376 1377 i2c-mux@74 { 1378 compatible = "nxp,pca9548"; 1379 #address-cells = <0x01>; 1380 #size-cells = <0x00>; 1381 reg = <0x74>; 1382 1383 i2c@0 { 1384 #address-cells = <0x01>; 1385 #size-cells = <0x00>; 1386 reg = <0x00>; 1387 1388 eeprom@54 { 1389 compatible = "atmel,24c08"; 1390 reg = <0x54>; 1391 #address-cells = <0x01>; 1392 #size-cells = <0x01>; 1393 phandle = <0x7a>; 1394 1395 board-sn@0 { 1396 reg = <0x00 0x14>; 1397 phandle = <0x7b>; 1398 }; 1399 1400 eth-mac@20 { 1401 reg = <0x20 0x06>; 1402 phandle = <0x7c>; 1403 }; 1404 1405 board-name@d0 { 1406 reg = <0xd0 0x06>; 1407 phandle = <0x7d>; 1408 }; 1409 1410 board-revision@e0 { 1411 reg = <0xe0 0x03>; 1412 phandle = <0x7e>; 1413 }; 1414 }; 1415 }; 1416 1417 i2c@1 { 1418 #address-cells = <0x01>; 1419 #size-cells = <0x00>; 1420 reg = <0x01>; 1421 1422 clock-generator@36 { 1423 compatible = "silabs,si5341"; 1424 reg = <0x36>; 1425 #clock-cells = <0x02>; 1426 #address-cells = <0x01>; 1427 #size-cells = <0x00>; 1428 clocks = <0x17>; 1429 clock-names = "xtal"; 1430 clock-output-names = "si5341"; 1431 phandle = <0x1b>; 1432 1433 out@0 { 1434 reg = <0x00>; 1435 always-on; 1436 phandle = <0x7f>; 1437 }; 1438 1439 out@2 { 1440 reg = <0x02>; 1441 always-on; 1442 phandle = <0x80>; 1443 }; 1444 1445 out@3 { 1446 reg = <0x03>; 1447 always-on; 1448 phandle = <0x81>; 1449 }; 1450 1451 out@4 { 1452 reg = <0x04>; 1453 always-on; 1454 phandle = <0x82>; 1455 }; 1456 1457 out@5 { 1458 reg = <0x05>; 1459 always-on; 1460 phandle = <0x83>; 1461 }; 1462 1463 out@6 { 1464 reg = <0x06>; 1465 always-on; 1466 phandle = <0x84>; 1467 }; 1468 1469 out@7 { 1470 reg = <0x07>; 1471 always-on; 1472 phandle = <0x85>; 1473 }; 1474 1475 out@9 { 1476 reg = <0x09>; 1477 always-on; 1478 phandle = <0x86>; 1479 }; 1480 }; 1481 }; 1482 1483 i2c@2 { 1484 #address-cells = <0x01>; 1485 #size-cells = <0x00>; 1486 reg = <0x02>; 1487 1488 clock-generator@5d { 1489 #clock-cells = <0x00>; 1490 compatible = "silabs,si570"; 1491 reg = <0x5d>; 1492 temperature-stability = <0x32>; 1493 factory-fout = <0x11e1a300>; 1494 clock-frequency = <0x11e1a300>; 1495 clock-output-names = "si570_user"; 1496 phandle = <0x87>; 1497 }; 1498 }; 1499 1500 i2c@3 { 1501 #address-cells = <0x01>; 1502 #size-cells = <0x00>; 1503 reg = <0x03>; 1504 1505 clock-generator@5d { 1506 #clock-cells = <0x00>; 1507 compatible = "silabs,si570"; 1508 reg = <0x5d>; 1509 temperature-stability = <0x32>; 1510 factory-fout = <0x9502f90>; 1511 clock-frequency = <0x8d9ee20>; 1512 clock-output-names = "si570_mgt"; 1513 phandle = <0x88>; 1514 }; 1515 }; 1516 1517 i2c@4 { 1518 #address-cells = <0x01>; 1519 #size-cells = <0x00>; 1520 reg = <0x04>; 1521 1522 clock-generator@69 { 1523 compatible = "silabs,si5328"; 1524 reg = <0x69>; 1525 #address-cells = <0x01>; 1526 #size-cells = <0x00>; 1527 #clock-cells = <0x01>; 1528 clocks = <0x18>; 1529 clock-names = "xtal"; 1530 clock-output-names = "si5328"; 1531 phandle = <0x89>; 1532 1533 clk0@0 { 1534 reg = <0x00>; 1535 clock-frequency = <0x19bfcc0>; 1536 phandle = <0x8a>; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 i2c-mux@75 { 1543 compatible = "nxp,pca9548"; 1544 #address-cells = <0x01>; 1545 #size-cells = <0x00>; 1546 reg = <0x75>; 1547 1548 i2c@0 { 1549 #address-cells = <0x01>; 1550 #size-cells = <0x00>; 1551 reg = <0x00>; 1552 1553 ad7291@2f { 1554 compatible = "adi,ad7291"; 1555 reg = <0x2f>; 1556 }; 1557 1558 eeprom@50 { 1559 compatible = "at24,24c02"; 1560 reg = <0x50>; 1561 }; 1562 }; 1563 1564 i2c@1 { 1565 #address-cells = <0x01>; 1566 #size-cells = <0x00>; 1567 reg = <0x01>; 1568 }; 1569 1570 i2c@2 { 1571 #address-cells = <0x01>; 1572 #size-cells = <0x00>; 1573 reg = <0x02>; 1574 }; 1575 1576 i2c@3 { 1577 #address-cells = <0x01>; 1578 #size-cells = <0x00>; 1579 reg = <0x03>; 1580 }; 1581 1582 i2c@4 { 1583 #address-cells = <0x01>; 1584 #size-cells = <0x00>; 1585 reg = <0x04>; 1586 }; 1587 1588 i2c@5 { 1589 #address-cells = <0x01>; 1590 #size-cells = <0x00>; 1591 reg = <0x05>; 1592 }; 1593 1594 i2c@6 { 1595 #address-cells = <0x01>; 1596 #size-cells = <0x00>; 1597 reg = <0x06>; 1598 }; 1599 1600 i2c@7 { 1601 #address-cells = <0x01>; 1602 #size-cells = <0x00>; 1603 reg = <0x07>; 1604 }; 1605 }; 1606 }; 1607 1608 memory-controller@ff960000 { 1609 compatible = "xlnx,zynqmp-ocmc-1.0"; 1610 reg = <0x00 0xff960000 0x00 0x1000>; 1611 interrupt-parent = <0x04>; 1612 interrupts = <0x00 0x0a 0x04>; 1613 phandle = <0x8b>; 1614 }; 1615 1616 perf-monitor@ffa00000 { 1617 compatible = "xlnx,axi-perf-monitor"; 1618 reg = <0x00 0xffa00000 0x00 0x10000>; 1619 interrupts = <0x00 0x19 0x04>; 1620 interrupt-parent = <0x04>; 1621 xlnx,enable-profile = <0x00>; 1622 xlnx,enable-trace = <0x00>; 1623 xlnx,num-monitor-slots = <0x01>; 1624 xlnx,enable-event-count = <0x01>; 1625 xlnx,enable-event-log = <0x01>; 1626 xlnx,have-sampled-metric-cnt = <0x01>; 1627 xlnx,num-of-counters = <0x08>; 1628 xlnx,metric-count-width = <0x20>; 1629 xlnx,metrics-sample-count-width = <0x20>; 1630 xlnx,global-count-width = <0x20>; 1631 xlnx,metric-count-scale = <0x01>; 1632 clocks = <0x03 0x1f>; 1633 phandle = <0x8c>; 1634 }; 1635 1636 perf-monitor@fd0b0000 { 1637 compatible = "xlnx,axi-perf-monitor"; 1638 reg = <0x00 0xfd0b0000 0x00 0x10000>; 1639 interrupts = <0x00 0x7b 0x04>; 1640 interrupt-parent = <0x04>; 1641 xlnx,enable-profile = <0x00>; 1642 xlnx,enable-trace = <0x00>; 1643 xlnx,num-monitor-slots = <0x06>; 1644 xlnx,enable-event-count = <0x01>; 1645 xlnx,enable-event-log = <0x00>; 1646 xlnx,have-sampled-metric-cnt = <0x01>; 1647 xlnx,num-of-counters = <0x0a>; 1648 xlnx,metric-count-width = <0x20>; 1649 xlnx,metrics-sample-count-width = <0x20>; 1650 xlnx,global-count-width = <0x20>; 1651 xlnx,metric-count-scale = <0x01>; 1652 clocks = <0x03 0x1c>; 1653 phandle = <0x8d>; 1654 }; 1655 1656 perf-monitor@fd490000 { 1657 compatible = "xlnx,axi-perf-monitor"; 1658 reg = <0x00 0xfd490000 0x00 0x10000>; 1659 interrupts = <0x00 0x7b 0x04>; 1660 interrupt-parent = <0x04>; 1661 xlnx,enable-profile = <0x00>; 1662 xlnx,enable-trace = <0x00>; 1663 xlnx,num-monitor-slots = <0x01>; 1664 xlnx,enable-event-count = <0x01>; 1665 xlnx,enable-event-log = <0x00>; 1666 xlnx,have-sampled-metric-cnt = <0x01>; 1667 xlnx,num-of-counters = <0x08>; 1668 xlnx,metric-count-width = <0x20>; 1669 xlnx,metrics-sample-count-width = <0x20>; 1670 xlnx,global-count-width = <0x20>; 1671 xlnx,metric-count-scale = <0x01>; 1672 clocks = <0x03 0x1c>; 1673 phandle = <0x8e>; 1674 }; 1675 1676 perf-monitor@ffa10000 { 1677 compatible = "xlnx,axi-perf-monitor"; 1678 reg = <0x00 0xffa10000 0x00 0x10000>; 1679 interrupts = <0x00 0x19 0x04>; 1680 interrupt-parent = <0x04>; 1681 xlnx,enable-profile = <0x00>; 1682 xlnx,enable-trace = <0x00>; 1683 xlnx,num-monitor-slots = <0x01>; 1684 xlnx,enable-event-count = <0x01>; 1685 xlnx,enable-event-log = <0x01>; 1686 xlnx,have-sampled-metric-cnt = <0x01>; 1687 xlnx,num-of-counters = <0x08>; 1688 xlnx,metric-count-width = <0x20>; 1689 xlnx,metrics-sample-count-width = <0x20>; 1690 xlnx,global-count-width = <0x20>; 1691 xlnx,metric-count-scale = <0x01>; 1692 clocks = <0x03 0x1f>; 1693 phandle = <0x8f>; 1694 }; 1695 1696 pcie@fd0e0000 { 1697 compatible = "xlnx,nwl-pcie-2.11"; 1698 status = "okay"; 1699 #address-cells = <0x03>; 1700 #size-cells = <0x02>; 1701 #interrupt-cells = <0x01>; 1702 msi-controller; 1703 device_type = "pci"; 1704 interrupt-parent = <0x04>; 1705 interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>; 1706 interrupt-names = "misc\0dummy\0intx\0msi1\0msi0"; 1707 msi-parent = <0x19>; 1708 reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>; 1709 reg-names = "breg\0pcireg\0cfg"; 1710 ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>; 1711 bus-range = <0x00 0xff>; 1712 interrupt-map-mask = <0x00 0x00 0x00 0x07>; 1713 interrupt-map = <0x00 0x00 0x00 0x01 0x1a 0x01 0x00 0x00 0x00 0x02 0x1a 0x02 0x00 0x00 0x00 0x03 0x1a 0x03 0x00 0x00 0x00 0x04 0x1a 0x04>; 1714 #stream-id-cells = <0x01>; 1715 iommus = <0x0e 0x4d0>; 1716 power-domains = <0x0c 0x3b>; 1717 clocks = <0x03 0x17>; 1718 phandle = <0x19>; 1719 1720 legacy-interrupt-controller { 1721 interrupt-controller; 1722 #address-cells = <0x00>; 1723 #interrupt-cells = <0x01>; 1724 phandle = <0x1a>; 1725 }; 1726 }; 1727 1728 spi@ff0f0000 { 1729 u-boot,dm-pre-reloc; 1730 compatible = "xlnx,zynqmp-qspi-1.0"; 1731 status = "okay"; 1732 clock-names = "ref_clk\0pclk"; 1733 interrupts = <0x00 0x0f 0x04>; 1734 interrupt-parent = <0x04>; 1735 num-cs = <0x01>; 1736 reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>; 1737 #address-cells = <0x01>; 1738 #size-cells = <0x00>; 1739 #stream-id-cells = <0x01>; 1740 iommus = <0x0e 0x873>; 1741 power-domains = <0x0c 0x2d>; 1742 clocks = <0x03 0x35 0x03 0x1f>; 1743 is-dual = <0x01>; 1744 phandle = <0x90>; 1745 1746 flash@0 { 1747 compatible = "m25p80\0jedec,spi-nor"; 1748 #address-cells = <0x01>; 1749 #size-cells = <0x01>; 1750 reg = <0x00>; 1751 spi-tx-bus-width = <0x01>; 1752 spi-rx-bus-width = <0x04>; 1753 spi-max-frequency = <0x66ff300>; 1754 1755 partition@0 { 1756 label = "qspi-fsbl-uboot"; 1757 reg = <0x00 0x100000>; 1758 }; 1759 1760 partition@100000 { 1761 label = "qspi-linux"; 1762 reg = <0x100000 0x500000>; 1763 }; 1764 1765 partition@600000 { 1766 label = "qspi-device-tree"; 1767 reg = <0x600000 0x20000>; 1768 }; 1769 1770 partition@620000 { 1771 label = "qspi-rootfs"; 1772 reg = <0x620000 0x5e0000>; 1773 }; 1774 }; 1775 }; 1776 1777 phy@fd400000 { 1778 compatible = "xlnx,zynqmp-psgtr-v1.1"; 1779 status = "okay"; 1780 reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>; 1781 reg-names = "serdes\0siou"; 1782 #phy-cells = <0x04>; 1783 clocks = <0x1b 0x00 0x05 0x1b 0x00 0x03 0x1b 0x00 0x02 0x1b 0x00 0x00>; 1784 clock-names = "ref0\0ref1\0ref2\0ref3"; 1785 phandle = <0x1d>; 1786 }; 1787 1788 rtc@ffa60000 { 1789 compatible = "xlnx,zynqmp-rtc"; 1790 status = "okay"; 1791 reg = <0x00 0xffa60000 0x00 0x100>; 1792 interrupt-parent = <0x04>; 1793 interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>; 1794 interrupt-names = "alarm\0sec"; 1795 calibration = <0x7fff>; 1796 phandle = <0x91>; 1797 }; 1798 1799 ahci@fd0c0000 { 1800 compatible = "ceva,ahci-1v84"; 1801 status = "okay"; 1802 reg = <0x00 0xfd0c0000 0x00 0x2000>; 1803 interrupt-parent = <0x04>; 1804 interrupts = <0x00 0x85 0x04>; 1805 power-domains = <0x0c 0x1c>; 1806 resets = <0x1c 0x10>; 1807 #stream-id-cells = <0x04>; 1808 clocks = <0x03 0x16>; 1809 ceva,p0-cominit-params = <0x18401828>; 1810 ceva,p0-comwake-params = <0x614080e>; 1811 ceva,p0-burst-params = <0x13084a06>; 1812 ceva,p0-retry-params = <0x96a43ffc>; 1813 ceva,p1-cominit-params = <0x18401828>; 1814 ceva,p1-comwake-params = <0x614080e>; 1815 ceva,p1-burst-params = <0x13084a06>; 1816 ceva,p1-retry-params = <0x96a43ffc>; 1817 phy-names = "sata-phy"; 1818 phys = <0x1d 0x03 0x01 0x01 0x01>; 1819 phandle = <0x92>; 1820 }; 1821 1822 mmc@ff160000 { 1823 u-boot,dm-pre-reloc; 1824 compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; 1825 status = "disabled"; 1826 interrupt-parent = <0x04>; 1827 interrupts = <0x00 0x30 0x04>; 1828 reg = <0x00 0xff160000 0x00 0x1000>; 1829 clock-names = "clk_xin\0clk_ahb"; 1830 xlnx,device_id = <0x00>; 1831 #stream-id-cells = <0x01>; 1832 iommus = <0x0e 0x870>; 1833 nvmem-cells = <0x1e>; 1834 nvmem-cell-names = "soc_revision"; 1835 #clock-cells = <0x01>; 1836 clock-output-names = "clk_out_sd0\0clk_in_sd0"; 1837 power-domains = <0x0c 0x27>; 1838 clocks = <0x03 0x36 0x03 0x1f>; 1839 phandle = <0x93>; 1840 }; 1841 1842 mmc@ff170000 { 1843 u-boot,dm-pre-reloc; 1844 compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; 1845 status = "okay"; 1846 interrupt-parent = <0x04>; 1847 interrupts = <0x00 0x31 0x04>; 1848 reg = <0x00 0xff170000 0x00 0x1000>; 1849 clock-names = "clk_xin\0clk_ahb"; 1850 xlnx,device_id = <0x01>; 1851 #stream-id-cells = <0x01>; 1852 iommus = <0x0e 0x871>; 1853 nvmem-cells = <0x1e>; 1854 nvmem-cell-names = "soc_revision"; 1855 #clock-cells = <0x01>; 1856 clock-output-names = "clk_out_sd1\0clk_in_sd1"; 1857 power-domains = <0x0c 0x28>; 1858 clocks = <0x03 0x37 0x03 0x1f>; 1859 no-1-8-v; 1860 pinctrl-names = "default"; 1861 pinctrl-0 = <0x1f>; 1862 xlnx,mio-bank = <0x01>; 1863 phandle = <0x94>; 1864 }; 1865 1866 spi@ff040000 { 1867 compatible = "cdns,spi-r1p6"; 1868 status = "okay"; 1869 interrupt-parent = <0x04>; 1870 interrupts = <0x00 0x13 0x04>; 1871 reg = <0x00 0xff040000 0x00 0x1000>; 1872 clock-names = "ref_clk\0pclk"; 1873 #address-cells = <0x01>; 1874 #size-cells = <0x00>; 1875 power-domains = <0x0c 0x23>; 1876 clocks = <0x03 0x3a 0x03 0x1f>; 1877 phandle = <0x95>; 1878 1879 ad9361-phy@0 { 1880 compatible = "adi,ad9361"; 1881 reg = <0x00>; 1882 spi-cpha; 1883 spi-max-frequency = <0x989680>; 1884 clocks = <0x20 0x00>; 1885 clock-names = "ad9361_ext_refclk"; 1886 clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; 1887 #clock-cells = <0x01>; 1888 adi,digital-interface-tune-skip-mode = <0x00>; 1889 adi,pp-tx-swap-enable; 1890 adi,pp-rx-swap-enable; 1891 adi,rx-frame-pulse-mode-enable; 1892 adi,lvds-mode-enable; 1893 adi,lvds-bias-mV = <0x96>; 1894 adi,lvds-rx-onchip-termination-enable; 1895 adi,rx-data-delay = <0x04>; 1896 adi,tx-fb-clock-delay = <0x07>; 1897 adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>; 1898 adi,2rx-2tx-mode-enable; 1899 adi,frequency-division-duplex-mode-enable; 1900 adi,rx-rf-port-input-select = <0x00>; 1901 adi,tx-rf-port-input-select = <0x00>; 1902 adi,tx-attenuation-mdB = <0x2710>; 1903 adi,tx-lo-powerdown-managed-enable; 1904 adi,rf-rx-bandwidth-hz = <0x112a880>; 1905 adi,rf-tx-bandwidth-hz = <0x112a880>; 1906 adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; 1907 adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; 1908 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 1909 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 1910 adi,gc-rx1-mode = <0x02>; 1911 adi,gc-rx2-mode = <0x02>; 1912 adi,gc-adc-ovr-sample-size = <0x04>; 1913 adi,gc-adc-small-overload-thresh = <0x2f>; 1914 adi,gc-adc-large-overload-thresh = <0x3a>; 1915 adi,gc-lmt-overload-high-thresh = <0x320>; 1916 adi,gc-lmt-overload-low-thresh = <0x2c0>; 1917 adi,gc-dec-pow-measurement-duration = <0x2000>; 1918 adi,gc-low-power-thresh = <0x18>; 1919 adi,mgc-inc-gain-step = <0x02>; 1920 adi,mgc-dec-gain-step = <0x02>; 1921 adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; 1922 adi,agc-attack-delay-extra-margin-us = <0x01>; 1923 adi,agc-outer-thresh-high = <0x05>; 1924 adi,agc-outer-thresh-high-dec-steps = <0x02>; 1925 adi,agc-inner-thresh-high = <0x0a>; 1926 adi,agc-inner-thresh-high-dec-steps = <0x01>; 1927 adi,agc-inner-thresh-low = <0x0c>; 1928 adi,agc-inner-thresh-low-inc-steps = <0x01>; 1929 adi,agc-outer-thresh-low = <0x12>; 1930 adi,agc-outer-thresh-low-inc-steps = <0x02>; 1931 adi,agc-adc-small-overload-exceed-counter = <0x0a>; 1932 adi,agc-adc-large-overload-exceed-counter = <0x0a>; 1933 adi,agc-adc-large-overload-inc-steps = <0x02>; 1934 adi,agc-lmt-overload-large-exceed-counter = <0x0a>; 1935 adi,agc-lmt-overload-small-exceed-counter = <0x0a>; 1936 adi,agc-lmt-overload-large-inc-steps = <0x02>; 1937 adi,agc-gain-update-interval-us = <0x3e8>; 1938 adi,fagc-dec-pow-measurement-duration = <0x40>; 1939 adi,fagc-lp-thresh-increment-steps = <0x01>; 1940 adi,fagc-lp-thresh-increment-time = <0x05>; 1941 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; 1942 adi,fagc-final-overrange-count = <0x03>; 1943 adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; 1944 adi,fagc-lmt-final-settling-steps = <0x01>; 1945 adi,fagc-lock-level = <0x0a>; 1946 adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; 1947 adi,fagc-lock-level-lmt-gain-increase-enable; 1948 adi,fagc-lpf-final-settling-steps = <0x01>; 1949 adi,fagc-optimized-gain-offset = <0x05>; 1950 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 1951 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 1952 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; 1953 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 1954 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; 1955 adi,fagc-rst-gla-large-adc-overload-enable; 1956 adi,fagc-rst-gla-large-lmt-overload-enable; 1957 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; 1958 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 1959 adi,fagc-state-wait-time-ns = <0x104>; 1960 adi,fagc-use-last-lock-level-for-set-gain-enable; 1961 adi,rssi-restart-mode = <0x03>; 1962 adi,rssi-delay = <0x01>; 1963 adi,rssi-wait = <0x01>; 1964 adi,rssi-duration = <0x3e8>; 1965 adi,ctrl-outs-index = <0x00>; 1966 adi,ctrl-outs-enable-mask = <0xff>; 1967 adi,temp-sense-measurement-interval-ms = <0x3e8>; 1968 adi,temp-sense-offset-signed = <0xce>; 1969 adi,temp-sense-periodic-measurement-enable; 1970 adi,aux-dac-manual-mode-enable; 1971 adi,aux-dac1-default-value-mV = <0x00>; 1972 adi,aux-dac1-rx-delay-us = <0x00>; 1973 adi,aux-dac1-tx-delay-us = <0x00>; 1974 adi,aux-dac2-default-value-mV = <0x00>; 1975 adi,aux-dac2-rx-delay-us = <0x00>; 1976 adi,aux-dac2-tx-delay-us = <0x00>; 1977 en_agc-gpios = <0x14 0x7a 0x00>; 1978 sync-gpios = <0x14 0x7b 0x00>; 1979 reset-gpios = <0x14 0x7c 0x00>; 1980 enable-gpios = <0x14 0x7d 0x00>; 1981 txnrx-gpios = <0x14 0x7e 0x00>; 1982 phandle = <0x3d>; 1983 }; 1984 }; 1985 1986 spi@ff050000 { 1987 compatible = "cdns,spi-r1p6"; 1988 status = "disabled"; 1989 interrupt-parent = <0x04>; 1990 interrupts = <0x00 0x14 0x04>; 1991 reg = <0x00 0xff050000 0x00 0x1000>; 1992 clock-names = "ref_clk\0pclk"; 1993 #address-cells = <0x01>; 1994 #size-cells = <0x00>; 1995 power-domains = <0x0c 0x24>; 1996 clocks = <0x03 0x3b 0x03 0x1f>; 1997 phandle = <0x96>; 1998 }; 1999 2000 timer@ff110000 { 2001 compatible = "cdns,ttc"; 2002 status = "disabled"; 2003 interrupt-parent = <0x04>; 2004 interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>; 2005 reg = <0x00 0xff110000 0x00 0x1000>; 2006 timer-width = <0x20>; 2007 power-domains = <0x0c 0x18>; 2008 clocks = <0x03 0x1f>; 2009 phandle = <0x97>; 2010 }; 2011 2012 timer@ff120000 { 2013 compatible = "cdns,ttc"; 2014 status = "disabled"; 2015 interrupt-parent = <0x04>; 2016 interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>; 2017 reg = <0x00 0xff120000 0x00 0x1000>; 2018 timer-width = <0x20>; 2019 power-domains = <0x0c 0x19>; 2020 clocks = <0x03 0x1f>; 2021 phandle = <0x98>; 2022 }; 2023 2024 timer@ff130000 { 2025 compatible = "cdns,ttc"; 2026 status = "disabled"; 2027 interrupt-parent = <0x04>; 2028 interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>; 2029 reg = <0x00 0xff130000 0x00 0x1000>; 2030 timer-width = <0x20>; 2031 power-domains = <0x0c 0x1a>; 2032 clocks = <0x03 0x1f>; 2033 phandle = <0x99>; 2034 }; 2035 2036 timer@ff140000 { 2037 compatible = "cdns,ttc"; 2038 status = "disabled"; 2039 interrupt-parent = <0x04>; 2040 interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>; 2041 reg = <0x00 0xff140000 0x00 0x1000>; 2042 timer-width = <0x20>; 2043 power-domains = <0x0c 0x1b>; 2044 clocks = <0x03 0x1f>; 2045 phandle = <0x9a>; 2046 }; 2047 2048 serial@ff000000 { 2049 u-boot,dm-pre-reloc; 2050 compatible = "cdns,uart-r1p12\0xlnx,xuartps"; 2051 status = "okay"; 2052 interrupt-parent = <0x04>; 2053 interrupts = <0x00 0x15 0x04>; 2054 reg = <0x00 0xff000000 0x00 0x1000>; 2055 clock-names = "uart_clk\0pclk"; 2056 power-domains = <0x0c 0x21>; 2057 clocks = <0x03 0x38 0x03 0x1f>; 2058 pinctrl-names = "default"; 2059 pinctrl-0 = <0x21>; 2060 phandle = <0x9b>; 2061 }; 2062 2063 serial@ff010000 { 2064 u-boot,dm-pre-reloc; 2065 compatible = "cdns,uart-r1p12\0xlnx,xuartps"; 2066 status = "okay"; 2067 interrupt-parent = <0x04>; 2068 interrupts = <0x00 0x16 0x04>; 2069 reg = <0x00 0xff010000 0x00 0x1000>; 2070 clock-names = "uart_clk\0pclk"; 2071 power-domains = <0x0c 0x22>; 2072 clocks = <0x03 0x39 0x03 0x1f>; 2073 pinctrl-names = "default"; 2074 pinctrl-0 = <0x22>; 2075 phandle = <0x9c>; 2076 }; 2077 2078 usb0@ff9d0000 { 2079 #address-cells = <0x02>; 2080 #size-cells = <0x02>; 2081 status = "okay"; 2082 compatible = "xlnx,zynqmp-dwc3"; 2083 reg = <0x00 0xff9d0000 0x00 0x100>; 2084 clock-names = "bus_clk\0ref_clk"; 2085 power-domains = <0x0c 0x16>; 2086 resets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>; 2087 reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; 2088 reset-gpio = <0x23 0x01 0x00>; 2089 ranges; 2090 nvmem-cells = <0x1e>; 2091 nvmem-cell-names = "soc_revision"; 2092 clocks = <0x03 0x20 0x03 0x22>; 2093 pinctrl-names = "default"; 2094 pinctrl-0 = <0x24>; 2095 phandle = <0x9d>; 2096 2097 dwc3@fe200000 { 2098 compatible = "snps,dwc3"; 2099 status = "okay"; 2100 reg = <0x00 0xfe200000 0x00 0x40000>; 2101 interrupt-parent = <0x04>; 2102 interrupt-names = "dwc_usb3\0otg\0hiber"; 2103 interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>; 2104 #stream-id-cells = <0x01>; 2105 iommus = <0x0e 0x860>; 2106 snps,quirk-frame-length-adjustment = <0x20>; 2107 snps,refclk_fladj; 2108 snps,enable_guctl1_resume_quirk; 2109 snps,enable_guctl1_ipd_quirk; 2110 snps,xhci-stream-quirk; 2111 dr_mode = "otg"; 2112 snps,usb3_lpm_capable; 2113 phy-names = "usb3-phy"; 2114 phys = <0x1d 0x02 0x04 0x00 0x02>; 2115 maximum-speed = "super-speed"; 2116 phandle = <0x9e>; 2117 }; 2118 }; 2119 2120 usb1@ff9e0000 { 2121 #address-cells = <0x02>; 2122 #size-cells = <0x02>; 2123 status = "disabled"; 2124 compatible = "xlnx,zynqmp-dwc3"; 2125 reg = <0x00 0xff9e0000 0x00 0x100>; 2126 clock-names = "bus_clk\0ref_clk"; 2127 power-domains = <0x0c 0x17>; 2128 resets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>; 2129 reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; 2130 ranges; 2131 nvmem-cells = <0x1e>; 2132 nvmem-cell-names = "soc_revision"; 2133 clocks = <0x03 0x21 0x03 0x22>; 2134 phandle = <0x9f>; 2135 2136 dwc3@fe300000 { 2137 compatible = "snps,dwc3"; 2138 status = "disabled"; 2139 reg = <0x00 0xfe300000 0x00 0x40000>; 2140 interrupt-parent = <0x04>; 2141 interrupt-names = "dwc_usb3\0otg\0hiber"; 2142 interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>; 2143 #stream-id-cells = <0x01>; 2144 iommus = <0x0e 0x861>; 2145 snps,quirk-frame-length-adjustment = <0x20>; 2146 snps,refclk_fladj; 2147 snps,enable_guctl1_resume_quirk; 2148 snps,enable_guctl1_ipd_quirk; 2149 snps,xhci-stream-quirk; 2150 phandle = <0xa0>; 2151 }; 2152 }; 2153 2154 watchdog@fd4d0000 { 2155 compatible = "cdns,wdt-r1p2"; 2156 status = "okay"; 2157 interrupt-parent = <0x04>; 2158 interrupts = <0x00 0x71 0x01>; 2159 reg = <0x00 0xfd4d0000 0x00 0x1000>; 2160 timeout-sec = <0x3c>; 2161 reset-on-timeout; 2162 clocks = <0x03 0x4b>; 2163 phandle = <0xa1>; 2164 }; 2165 2166 watchdog@ff150000 { 2167 compatible = "cdns,wdt-r1p2"; 2168 status = "disabled"; 2169 interrupt-parent = <0x04>; 2170 interrupts = <0x00 0x34 0x01>; 2171 reg = <0x00 0xff150000 0x00 0x1000>; 2172 timeout-sec = <0x0a>; 2173 clocks = <0x03 0x70>; 2174 phandle = <0xa2>; 2175 }; 2176 2177 ams@ffa50000 { 2178 compatible = "xlnx,zynqmp-ams"; 2179 status = "okay"; 2180 interrupt-parent = <0x04>; 2181 interrupts = <0x00 0x38 0x04>; 2182 interrupt-names = "ams-irq"; 2183 reg = <0x00 0xffa50000 0x00 0x800>; 2184 reg-names = "ams-base"; 2185 #address-cells = <0x02>; 2186 #size-cells = <0x02>; 2187 #io-channel-cells = <0x01>; 2188 ranges; 2189 clocks = <0x03 0x46>; 2190 phandle = <0xa3>; 2191 2192 ams_ps@ffa50800 { 2193 compatible = "xlnx,zynqmp-ams-ps"; 2194 status = "okay"; 2195 reg = <0x00 0xffa50800 0x00 0x400>; 2196 phandle = <0xa4>; 2197 }; 2198 2199 ams_pl@ffa50c00 { 2200 compatible = "xlnx,zynqmp-ams-pl"; 2201 status = "okay"; 2202 reg = <0x00 0xffa50c00 0x00 0x400>; 2203 phandle = <0xa5>; 2204 }; 2205 }; 2206 2207 dma-controller@fd4c0000 { 2208 compatible = "xlnx,zynqmp-dpdma"; 2209 status = "okay"; 2210 reg = <0x00 0xfd4c0000 0x00 0x1000>; 2211 interrupts = <0x00 0x7a 0x04>; 2212 interrupt-parent = <0x04>; 2213 clock-names = "axi_clk"; 2214 power-domains = <0x0c 0x29>; 2215 dma-channels = <0x06>; 2216 #stream-id-cells = <0x01>; 2217 iommus = <0x0e 0xce4>; 2218 #dma-cells = <0x01>; 2219 clocks = <0x03 0x14>; 2220 phandle = <0x25>; 2221 }; 2222 2223 display@fd4a0000 { 2224 compatible = "xlnx,zynqmp-dpsub-1.7"; 2225 status = "okay"; 2226 reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>; 2227 reg-names = "dp\0blend\0av_buf\0aud"; 2228 interrupts = <0x00 0x77 0x04>; 2229 interrupt-parent = <0x04>; 2230 #stream-id-cells = <0x01>; 2231 iommus = <0x0e 0xce3>; 2232 clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in"; 2233 power-domains = <0x0c 0x29>; 2234 resets = <0x1c 0x03>; 2235 dma-names = "vid0\0vid1\0vid2\0gfx0"; 2236 dmas = <0x25 0x00 0x25 0x01 0x25 0x02 0x25 0x03>; 2237 clocks = <0x26 0x03 0x11 0x03 0x10>; 2238 phy-names = "dp-phy0"; 2239 phys = <0x1d 0x01 0x06 0x00 0x03>; 2240 phandle = <0xa6>; 2241 2242 i2c-bus { 2243 }; 2244 2245 zynqmp_dp_snd_codec0 { 2246 compatible = "xlnx,dp-snd-codec"; 2247 clock-names = "aud_clk"; 2248 clocks = <0x03 0x11>; 2249 status = "okay"; 2250 phandle = <0x29>; 2251 }; 2252 2253 zynqmp_dp_snd_pcm0 { 2254 compatible = "xlnx,dp-snd-pcm"; 2255 dmas = <0x25 0x04>; 2256 dma-names = "tx"; 2257 status = "okay"; 2258 phandle = <0x27>; 2259 }; 2260 2261 zynqmp_dp_snd_pcm1 { 2262 compatible = "xlnx,dp-snd-pcm"; 2263 dmas = <0x25 0x05>; 2264 dma-names = "tx"; 2265 status = "okay"; 2266 phandle = <0x28>; 2267 }; 2268 2269 zynqmp_dp_snd_card { 2270 compatible = "xlnx,dp-snd-card"; 2271 xlnx,dp-snd-pcm = <0x27 0x28>; 2272 xlnx,dp-snd-codec = <0x29>; 2273 status = "okay"; 2274 phandle = <0xa7>; 2275 }; 2276 }; 2277 }; 2278 2279 fclk0 { 2280 status = "okay"; 2281 compatible = "xlnx,fclk"; 2282 clocks = <0x03 0x47>; 2283 phandle = <0xa8>; 2284 }; 2285 2286 fclk1 { 2287 status = "okay"; 2288 compatible = "xlnx,fclk"; 2289 clocks = <0x03 0x48>; 2290 phandle = <0xa9>; 2291 }; 2292 2293 fclk2 { 2294 status = "okay"; 2295 compatible = "xlnx,fclk"; 2296 clocks = <0x03 0x49>; 2297 phandle = <0xaa>; 2298 }; 2299 2300 fclk3 { 2301 status = "okay"; 2302 compatible = "xlnx,fclk"; 2303 clocks = <0x03 0x4a>; 2304 phandle = <0xab>; 2305 }; 2306 2307 pss_ref_clk { 2308 u-boot,dm-pre-reloc; 2309 compatible = "fixed-clock"; 2310 #clock-cells = <0x00>; 2311 clock-frequency = <0x1fca055>; 2312 phandle = <0x06>; 2313 }; 2314 2315 video_clk { 2316 u-boot,dm-pre-reloc; 2317 compatible = "fixed-clock"; 2318 #clock-cells = <0x00>; 2319 clock-frequency = <0x19bfcc0>; 2320 phandle = <0x07>; 2321 }; 2322 2323 pss_alt_ref_clk { 2324 u-boot,dm-pre-reloc; 2325 compatible = "fixed-clock"; 2326 #clock-cells = <0x00>; 2327 clock-frequency = <0x00>; 2328 phandle = <0x08>; 2329 }; 2330 2331 gt_crx_ref_clk { 2332 u-boot,dm-pre-reloc; 2333 compatible = "fixed-clock"; 2334 #clock-cells = <0x00>; 2335 clock-frequency = <0x66ff300>; 2336 phandle = <0x0a>; 2337 }; 2338 2339 aux_ref_clk { 2340 u-boot,dm-pre-reloc; 2341 compatible = "fixed-clock"; 2342 #clock-cells = <0x00>; 2343 clock-frequency = <0x19bfcc0>; 2344 phandle = <0x09>; 2345 }; 2346 2347 dp_aclk { 2348 compatible = "fixed-clock"; 2349 #clock-cells = <0x00>; 2350 clock-frequency = <0x5f5e100>; 2351 clock-accuracy = <0x64>; 2352 phandle = <0x26>; 2353 }; 2354 2355 aliases { 2356 ethernet0 = "/axi/ethernet@ff0e0000"; 2357 gpio0 = "/axi/gpio@ff0a0000"; 2358 i2c0 = "/axi/i2c@ff020000"; 2359 i2c1 = "/axi/i2c@ff030000"; 2360 mmc0 = "/axi/mmc@ff170000"; 2361 rtc0 = "/axi/rtc@ffa60000"; 2362 serial0 = "/axi/serial@ff000000"; 2363 serial1 = "/axi/serial@ff010000"; 2364 serial2 = "/dcc"; 2365 spi0 = "/axi/spi@ff0f0000"; 2366 usb0 = "/axi/usb0@ff9d0000"; 2367 }; 2368 2369 chosen { 2370 bootargs = "earlycon"; 2371 stdout-path = "serial0:115200n8"; 2372 xlnx,eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54"; 2373 }; 2374 2375 memory@0 { 2376 device_type = "memory"; 2377 reg = <0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000>; 2378 }; 2379 2380 gpio-keys { 2381 compatible = "gpio-keys"; 2382 autorepeat; 2383 2384 sw19 { 2385 label = "sw19"; 2386 gpios = <0x14 0x16 0x00>; 2387 linux,code = <0x6c>; 2388 wakeup-source; 2389 autorepeat; 2390 }; 2391 }; 2392 2393 leds { 2394 compatible = "gpio-leds"; 2395 2396 heartbeat-led { 2397 label = "heartbeat"; 2398 gpios = <0x14 0x17 0x00>; 2399 linux,default-trigger = "heartbeat"; 2400 }; 2401 }; 2402 2403 ina226-u76 { 2404 compatible = "iio-hwmon"; 2405 io-channels = <0x2a 0x00 0x2a 0x01 0x2a 0x02 0x2a 0x03>; 2406 }; 2407 2408 ina226-u77 { 2409 compatible = "iio-hwmon"; 2410 io-channels = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03>; 2411 }; 2412 2413 ina226-u78 { 2414 compatible = "iio-hwmon"; 2415 io-channels = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03>; 2416 }; 2417 2418 ina226-u87 { 2419 compatible = "iio-hwmon"; 2420 io-channels = <0x2d 0x00 0x2d 0x01 0x2d 0x02 0x2d 0x03>; 2421 }; 2422 2423 ina226-u85 { 2424 compatible = "iio-hwmon"; 2425 io-channels = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03>; 2426 }; 2427 2428 ina226-u86 { 2429 compatible = "iio-hwmon"; 2430 io-channels = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>; 2431 }; 2432 2433 ina226-u93 { 2434 compatible = "iio-hwmon"; 2435 io-channels = <0x30 0x00 0x30 0x01 0x30 0x02 0x30 0x03>; 2436 }; 2437 2438 ina226-u88 { 2439 compatible = "iio-hwmon"; 2440 io-channels = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>; 2441 }; 2442 2443 ina226-u15 { 2444 compatible = "iio-hwmon"; 2445 io-channels = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>; 2446 }; 2447 2448 ina226-u92 { 2449 compatible = "iio-hwmon"; 2450 io-channels = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03>; 2451 }; 2452 2453 ina226-u79 { 2454 compatible = "iio-hwmon"; 2455 io-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>; 2456 }; 2457 2458 ina226-u81 { 2459 compatible = "iio-hwmon"; 2460 io-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>; 2461 }; 2462 2463 ina226-u80 { 2464 compatible = "iio-hwmon"; 2465 io-channels = <0x36 0x00 0x36 0x01 0x36 0x02 0x36 0x03>; 2466 }; 2467 2468 ina226-u84 { 2469 compatible = "iio-hwmon"; 2470 io-channels = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>; 2471 }; 2472 2473 ina226-u16 { 2474 compatible = "iio-hwmon"; 2475 io-channels = <0x38 0x00 0x38 0x01 0x38 0x02 0x38 0x03>; 2476 }; 2477 2478 ina226-u65 { 2479 compatible = "iio-hwmon"; 2480 io-channels = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03>; 2481 }; 2482 2483 ina226-u74 { 2484 compatible = "iio-hwmon"; 2485 io-channels = <0x3a 0x00 0x3a 0x01 0x3a 0x02 0x3a 0x03>; 2486 }; 2487 2488 ina226-u75 { 2489 compatible = "iio-hwmon"; 2490 io-channels = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03>; 2491 }; 2492 2493 ref48M { 2494 compatible = "fixed-clock"; 2495 #clock-cells = <0x00>; 2496 clock-frequency = <0x2dc6c00>; 2497 phandle = <0x17>; 2498 }; 2499 2500 refhdmi { 2501 compatible = "fixed-clock"; 2502 #clock-cells = <0x00>; 2503 clock-frequency = <0x6cfd9c8>; 2504 phandle = <0x18>; 2505 }; 2506 2507 fpga-axi@0 { 2508 interrupt-parent = <0x04>; 2509 compatible = "simple-bus"; 2510 #address-cells = <0x01>; 2511 #size-cells = <0x01>; 2512 ranges = <0x00 0x00 0x00 0xffffffff>; 2513 phandle = <0xac>; 2514 2515 // dma@9c400000 { 2516 // compatible = "adi,axi-dmac-1.00.a"; 2517 // reg = <0x9c400000 0x10000>; 2518 // #dma-cells = <0x01>; 2519 // #clock-cells = <0x00>; 2520 // interrupts = <0x00 0x6d 0x04>; 2521 // clocks = <0x03 0x47>; 2522 // phandle = <0x3c>; 2523 2524 // adi,channels { 2525 // #size-cells = <0x00>; 2526 // #address-cells = <0x01>; 2527 2528 // dma-channel@0 { 2529 // reg = <0x00>; 2530 // adi,source-bus-width = <0x40>; 2531 // adi,source-bus-type = <0x02>; 2532 // adi,destination-bus-width = <0x40>; 2533 // adi,destination-bus-type = <0x00>; 2534 // }; 2535 // }; 2536 // }; 2537 2538 // dma@9c420000 { 2539 // compatible = "adi,axi-dmac-1.00.a"; 2540 // reg = <0x9c420000 0x10000>; 2541 // #dma-cells = <0x01>; 2542 // #clock-cells = <0x00>; 2543 // interrupts = <0x00 0x6c 0x04>; 2544 // clocks = <0x03 0x47>; 2545 // phandle = <0x3e>; 2546 2547 // adi,channels { 2548 // #size-cells = <0x00>; 2549 // #address-cells = <0x01>; 2550 2551 // dma-channel@0 { 2552 // reg = <0x00>; 2553 // adi,source-bus-width = <0x40>; 2554 // adi,source-bus-type = <0x00>; 2555 // adi,destination-bus-width = <0x40>; 2556 // adi,destination-bus-type = <0x02>; 2557 // }; 2558 // }; 2559 // }; 2560 2561 sdr: sdr { 2562 compatible ="sdr,sdr"; 2563 dmas = <&rx_dma 1 2564 &tx_dma 0>; 2565 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 2566 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt_useless", "tx_itrpt"; 2567 interrupts = <0 89 1 0 90 1 0 93 1 0 94 1>; 2568 } ; 2569 2570 axidmatest_1: axidmatest@1 { 2571 compatible ="xlnx,axi-dma-test-1.00.a"; 2572 dmas = <&rx_dma 0 2573 &rx_dma 1>; 2574 dma-names = "axidma0", "axidma1"; 2575 } ; 2576 2577 openwifi_ip_axi_bram_ctrl_0: axi_bram_ctrl@b0000000 { 2578 clock-names = "s_axi_aclk"; 2579 clocks = <0x3 0x49>; 2580 compatible = "xlnx,axi-bram-ctrl-4.1"; 2581 reg = <0x0 0xb0000000 0x0 0x80000>; 2582 xlnx,bram-addr-width = <0x10>; 2583 xlnx,bram-inst-mode = "EXTERNAL"; 2584 xlnx,ecc = <0x0>; 2585 xlnx,ecc-onoff-reset-value = <0x0>; 2586 xlnx,ecc-type = <0x0>; 2587 xlnx,fault-inject = <0x0>; 2588 xlnx,memory-depth = <0x10000>; 2589 xlnx,rd-cmd-optimization = <0x1>; 2590 xlnx,read-latency = <0x1>; 2591 xlnx,s-axi-ctrl-addr-width = <0x20>; 2592 xlnx,s-axi-ctrl-data-width = <0x20>; 2593 xlnx,s-axi-id-width = <0x10>; 2594 xlnx,s-axi-supports-narrow-burst = <0x1>; 2595 xlnx,single-port-bram = <0x1>; 2596 }; 2597 2598 tx_dma: dma@a0000000 { 2599 #dma-cells = <1>; 2600 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 2601 clocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>; 2602 compatible = "xlnx,axi-dma-1.00.a"; 2603 interrupt-names = "mm2s_introut", "s2mm_introut"; 2604 interrupts = <0 95 4 0 96 4>; 2605 reg = <0xA0000000 0x10000>; 2606 xlnx,addrwidth = <0x28>; 2607 xlnx,include-sg ; 2608 xlnx,sg-length-width = <0xe>; 2609 dma-channel@a0000000 { 2610 compatible = "xlnx,axi-dma-mm2s-channel"; 2611 dma-channels = <0x1>; 2612 interrupts = <0 95 4>; 2613 xlnx,datawidth = <0x40>; 2614 xlnx,device-id = <0x0>; 2615 }; 2616 dma-channel@A0000030 { 2617 compatible = "xlnx,axi-dma-s2mm-channel"; 2618 dma-channels = <0x1>; 2619 interrupts = <0 96 4>; 2620 xlnx,datawidth = <0x40>; 2621 xlnx,device-id = <0x0>; 2622 }; 2623 }; 2624 2625 rx_dma: dma@a0010000 { 2626 #dma-cells = <1>; 2627 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 2628 clocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>; 2629 compatible = "xlnx,axi-dma-1.00.a"; 2630 //dma-coherent ; 2631 interrupt-names = "mm2s_introut", "s2mm_introut"; 2632 interrupts = <0 91 4 0 92 4>; 2633 reg = <0xa0010000 0x10000>; 2634 xlnx,addrwidth = <0x28>; 2635 xlnx,include-sg ; 2636 xlnx,sg-length-width = <0xe>; 2637 dma-channel@a0010000 { 2638 compatible = "xlnx,axi-dma-mm2s-channel"; 2639 dma-channels = <0x1>; 2640 interrupts = <0 91 4>; 2641 xlnx,datawidth = <0x40>; 2642 xlnx,device-id = <0x1>; 2643 }; 2644 dma-channel@A0001030 { 2645 compatible = "xlnx,axi-dma-s2mm-channel"; 2646 dma-channels = <0x1>; 2647 interrupts = <0 92 4>; 2648 xlnx,datawidth = <0x40>; 2649 xlnx,device-id = <0x1>; 2650 }; 2651 }; 2652 2653 tx_intf_0: tx_intf@a0060000 { 2654 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 2655 clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>, <0x3 0x49>; 2656 compatible = "sdr,tx_intf"; 2657 interrupt-names = "tx_itrpt"; 2658 interrupts = <0 94 1>; 2659 reg = <0xa0060000 0x10000>; 2660 xlnx,s00-axi-addr-width = <0x7>; 2661 xlnx,s00-axi-data-width = <0x20>; 2662 }; 2663 2664 rx_intf_0: rx_intf@a0040000 { 2665 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 2666 clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>; 2667 compatible = "sdr,rx_intf"; 2668 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 2669 interrupts = <0 89 1 0 90 1>; 2670 reg = <0xa0040000 0x10000>; 2671 xlnx,s00-axi-addr-width = <0x7>; 2672 xlnx,s00-axi-data-width = <0x20>; 2673 }; 2674 2675 openofdm_tx_0: openofdm_tx@a0030000 { 2676 clock-names = "clk"; 2677 clocks = <0x3 0x49>; 2678 compatible = "sdr,openofdm_tx"; 2679 reg = <0xa0030000 0x10000>; 2680 }; 2681 2682 openofdm_rx_0: openofdm_rx@a0020000 { 2683 clock-names = "clk"; 2684 clocks = <0x3 0x49>; 2685 compatible = "sdr,openofdm_rx"; 2686 reg = <0xa0020000 0x10000>; 2687 }; 2688 2689 xpu_0: xpu@a0070000 { 2690 clock-names = "s00_axi_aclk"; 2691 clocks = <0x3 0x49>; 2692 compatible = "sdr,xpu"; 2693 reg = <0xa0070000 0x10000>; 2694 }; 2695 2696 side_ch_0: side_ch@a0050000 { 2697 clock-names = "s00_axi_aclk"; 2698 clocks = <0x3 0x49>; 2699 compatible = "sdr,side_ch"; 2700 reg = <0xa0050000 0x10000>; 2701 dmas = <&rx_dma 0 2702 &tx_dma 1>; 2703 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 2704 }; 2705 2706 cf-ad9361-lpc@99020000 { 2707 compatible = "adi,axi-ad9361-6.00.a"; 2708 reg = <0x99020000 0x6000>; 2709 // dmas = <0x3c 0x00>; 2710 // dma-names = "rx"; 2711 spibus-connected = <0x3d>; 2712 phandle = <0xad>; 2713 }; 2714 2715 cf-ad9361-dds-core-lpc@99024000 { 2716 compatible = "adi,axi-ad9361-dds-6.00.a"; 2717 reg = <0x99024000 0x1000>; 2718 clocks = <0x3d 0x0d>; 2719 clock-names = "sampl_clk"; 2720 // dmas = <0x3e 0x00>; 2721 // dma-names = "tx"; 2722 phandle = <0xae>; 2723 }; 2724 2725 // axi-sysid-0@85000000 { 2726 // compatible = "adi,axi-sysid-1.00.a"; 2727 // reg = <0x85000000 0x10000>; 2728 // phandle = <0xaf>; 2729 // }; 2730 }; 2731 2732 clocks { 2733 2734 clock@0 { 2735 compatible = "fixed-clock"; 2736 clock-frequency = <0x2625a00>; 2737 clock-output-names = "ad9361_ext_refclk"; 2738 #clock-cells = <0x00>; 2739 phandle = <0x20>; 2740 }; 2741 }; 2742 2743 __symbols__ { 2744 cpu0 = "/cpus/cpu@0"; 2745 cpu1 = "/cpus/cpu@1"; 2746 cpu2 = "/cpus/cpu@2"; 2747 cpu3 = "/cpus/cpu@3"; 2748 CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0"; 2749 cpu_opp_table = "/cpu-opp-table"; 2750 zynqmp_ipi = "/zynqmp_ipi"; 2751 ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400"; 2752 dcc = "/dcc"; 2753 zynqmp_firmware = "/firmware/zynqmp-firmware"; 2754 zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power"; 2755 soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0"; 2756 efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c"; 2757 efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20"; 2758 efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24"; 2759 efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28"; 2760 efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c"; 2761 efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30"; 2762 efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34"; 2763 efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38"; 2764 efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c"; 2765 efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40"; 2766 efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50"; 2767 efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54"; 2768 efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58"; 2769 efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c"; 2770 efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0"; 2771 efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0"; 2772 zynqmp_pcap = "/firmware/zynqmp-firmware/pcap"; 2773 xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes"; 2774 zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller"; 2775 pinctrl0 = "/firmware/zynqmp-firmware/pinctrl"; 2776 pinctrl_i2c0_default = "/firmware/zynqmp-firmware/pinctrl/i2c0-default"; 2777 pinctrl_i2c0_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c0-gpio"; 2778 pinctrl_i2c1_default = "/firmware/zynqmp-firmware/pinctrl/i2c1-default"; 2779 pinctrl_i2c1_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c1-gpio"; 2780 pinctrl_uart0_default = "/firmware/zynqmp-firmware/pinctrl/uart0-default"; 2781 pinctrl_uart1_default = "/firmware/zynqmp-firmware/pinctrl/uart1-default"; 2782 pinctrl_usb0_default = "/firmware/zynqmp-firmware/pinctrl/usb0-default"; 2783 pinctrl_gem3_default = "/firmware/zynqmp-firmware/pinctrl/gem3-default"; 2784 pinctrl_can1_default = "/firmware/zynqmp-firmware/pinctrl/can1-default"; 2785 pinctrl_sdhci1_default = "/firmware/zynqmp-firmware/pinctrl/sdhci1-default"; 2786 pinctrl_gpio_default = "/firmware/zynqmp-firmware/pinctrl/gpio-default"; 2787 xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384"; 2788 xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa"; 2789 modepin_gpio = "/firmware/zynqmp-firmware/gpio"; 2790 zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller"; 2791 fpga_full = "/fpga-full"; 2792 smmu = "/smmu@fd800000"; 2793 amba = "/axi"; 2794 can0 = "/axi/can@ff060000"; 2795 can1 = "/axi/can@ff070000"; 2796 cci = "/axi/cci@fd6e0000"; 2797 fpd_dma_chan1 = "/axi/dma@fd500000"; 2798 fpd_dma_chan2 = "/axi/dma@fd510000"; 2799 fpd_dma_chan3 = "/axi/dma@fd520000"; 2800 fpd_dma_chan4 = "/axi/dma@fd530000"; 2801 fpd_dma_chan5 = "/axi/dma@fd540000"; 2802 fpd_dma_chan6 = "/axi/dma@fd550000"; 2803 fpd_dma_chan7 = "/axi/dma@fd560000"; 2804 fpd_dma_chan8 = "/axi/dma@fd570000"; 2805 gic = "/axi/interrupt-controller@f9010000"; 2806 gpu = "/axi/gpu@fd4b0000"; 2807 lpd_dma_chan1 = "/axi/dma@ffa80000"; 2808 lpd_dma_chan2 = "/axi/dma@ffa90000"; 2809 lpd_dma_chan3 = "/axi/dma@ffaa0000"; 2810 lpd_dma_chan4 = "/axi/dma@ffab0000"; 2811 lpd_dma_chan5 = "/axi/dma@ffac0000"; 2812 lpd_dma_chan6 = "/axi/dma@ffad0000"; 2813 lpd_dma_chan7 = "/axi/dma@ffae0000"; 2814 lpd_dma_chan8 = "/axi/dma@ffaf0000"; 2815 mc = "/axi/memory-controller@fd070000"; 2816 nand0 = "/axi/nand-controller@ff100000"; 2817 gem0 = "/axi/ethernet@ff0b0000"; 2818 gem1 = "/axi/ethernet@ff0c0000"; 2819 gem2 = "/axi/ethernet@ff0d0000"; 2820 gem3 = "/axi/ethernet@ff0e0000"; 2821 phyc = "/axi/ethernet@ff0e0000/ethernet-phy@c"; 2822 gpio = "/axi/gpio@ff0a0000"; 2823 i2c0 = "/axi/i2c@ff020000"; 2824 tca6416_u97 = "/axi/i2c@ff020000/gpio@20"; 2825 tca6416_u61 = "/axi/i2c@ff020000/gpio@21"; 2826 u76 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@40"; 2827 u77 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@41"; 2828 u78 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@42"; 2829 u87 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@43"; 2830 u85 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@44"; 2831 u86 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@45"; 2832 u93 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@46"; 2833 u88 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@47"; 2834 u15 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4a"; 2835 u92 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4b"; 2836 u79 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@40"; 2837 u81 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@41"; 2838 u80 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@42"; 2839 u84 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@43"; 2840 u16 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@44"; 2841 u65 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@45"; 2842 u74 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@46"; 2843 u75 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@47"; 2844 i2c1 = "/axi/i2c@ff030000"; 2845 eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54"; 2846 board_sn = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-sn@0"; 2847 eth_mac = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/eth-mac@20"; 2848 board_name = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-name@d0"; 2849 board_revision = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-revision@e0"; 2850 si5341 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36"; 2851 si5341_0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@0"; 2852 si5341_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@2"; 2853 si5341_3 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@3"; 2854 si5341_4 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@4"; 2855 si5341_5 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@5"; 2856 si5341_6 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@6"; 2857 si5341_7 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@7"; 2858 si5341_9 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@9"; 2859 si570_1 = "/axi/i2c@ff030000/i2c-mux@74/i2c@2/clock-generator@5d"; 2860 si570_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d"; 2861 si5328 = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69"; 2862 si5328_clk = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69/clk0@0"; 2863 ocm = "/axi/memory-controller@ff960000"; 2864 perf_monitor_ocm = "/axi/perf-monitor@ffa00000"; 2865 perf_monitor_ddr = "/axi/perf-monitor@fd0b0000"; 2866 perf_monitor_cci = "/axi/perf-monitor@fd490000"; 2867 perf_monitor_lpd = "/axi/perf-monitor@ffa10000"; 2868 pcie = "/axi/pcie@fd0e0000"; 2869 pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller"; 2870 qspi = "/axi/spi@ff0f0000"; 2871 psgtr = "/axi/phy@fd400000"; 2872 rtc = "/axi/rtc@ffa60000"; 2873 sata = "/axi/ahci@fd0c0000"; 2874 sdhci0 = "/axi/mmc@ff160000"; 2875 sdhci1 = "/axi/mmc@ff170000"; 2876 spi0 = "/axi/spi@ff040000"; 2877 adc0_ad9361 = "/axi/spi@ff040000/ad9361-phy@0"; 2878 spi1 = "/axi/spi@ff050000"; 2879 ttc0 = "/axi/timer@ff110000"; 2880 ttc1 = "/axi/timer@ff120000"; 2881 ttc2 = "/axi/timer@ff130000"; 2882 ttc3 = "/axi/timer@ff140000"; 2883 uart0 = "/axi/serial@ff000000"; 2884 uart1 = "/axi/serial@ff010000"; 2885 usb0 = "/axi/usb0@ff9d0000"; 2886 dwc3_0 = "/axi/usb0@ff9d0000/dwc3@fe200000"; 2887 usb1 = "/axi/usb1@ff9e0000"; 2888 dwc3_1 = "/axi/usb1@ff9e0000/dwc3@fe300000"; 2889 watchdog0 = "/axi/watchdog@fd4d0000"; 2890 lpd_watchdog = "/axi/watchdog@ff150000"; 2891 xilinx_ams = "/axi/ams@ffa50000"; 2892 ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800"; 2893 ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00"; 2894 zynqmp_dpdma = "/axi/dma-controller@fd4c0000"; 2895 zynqmp_dpsub = "/axi/display@fd4a0000"; 2896 zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0"; 2897 zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0"; 2898 zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1"; 2899 zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card"; 2900 fclk0 = "/fclk0"; 2901 fclk1 = "/fclk1"; 2902 fclk2 = "/fclk2"; 2903 fclk3 = "/fclk3"; 2904 pss_ref_clk = "/pss_ref_clk"; 2905 video_clk = "/video_clk"; 2906 pss_alt_ref_clk = "/pss_alt_ref_clk"; 2907 gt_crx_ref_clk = "/gt_crx_ref_clk"; 2908 aux_ref_clk = "/aux_ref_clk"; 2909 dp_aclk = "/dp_aclk"; 2910 ref48 = "/ref48M"; 2911 refhdmi = "/refhdmi"; 2912 fpga_axi = "/fpga-axi@0"; 2913 rx_dma = "/fpga-axi@0/dma@9c400000"; 2914 tx_dma = "/fpga-axi@0/dma@9c420000"; 2915 cf_ad9361_adc_core_0 = "/fpga-axi@0/cf-ad9361-lpc@99020000"; 2916 cf_ad9361_dac_core_0 = "/fpga-axi@0/cf-ad9361-dds-core-lpc@99024000"; 2917 axi_sysid_0 = "/fpga-axi@0/axi-sysid-0@85000000"; 2918 ad9361_clkin = "/clocks/clock@0"; 2919 }; 2920}; 2921