1/dts-v1/; 2 3/ { 4 #address-cells = <0x1>; 5 #size-cells = <0x1>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x1>; 8 model = "Xilinx Zynq ZC702"; 9 10 cpus { 11 #address-cells = <0x1>; 12 #size-cells = <0x0>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x0>; 18 clocks = <0x2 0x3>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x3>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 }; 23 24 cpu@1 { 25 compatible = "arm,cortex-a9"; 26 device_type = "cpu"; 27 reg = <0x1>; 28 clocks = <0x2 0x3>; 29 }; 30 }; 31 32 fpga-full { 33 compatible = "fpga-region"; 34 fpga-mgr = <0x4>; 35 #address-cells = <0x1>; 36 #size-cells = <0x1>; 37 ranges; 38 }; 39 40 pmu@f8891000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; 43 interrupt-parent = <0x1>; 44 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 45 }; 46 47 fixedregulator { 48 compatible = "regulator-fixed"; 49 regulator-name = "VCCPINT"; 50 regulator-min-microvolt = <0xf4240>; 51 regulator-max-microvolt = <0xf4240>; 52 regulator-boot-on; 53 regulator-always-on; 54 linux,phandle = <0x3>; 55 phandle = <0x3>; 56 }; 57 58 amba { 59 u-boot,dm-pre-reloc; 60 compatible = "simple-bus"; 61 #address-cells = <0x1>; 62 #size-cells = <0x1>; 63 interrupt-parent = <0x1>; 64 ranges; 65 66 adc@f8007100 { 67 compatible = "xlnx,zynq-xadc-1.00.a"; 68 reg = <0xf8007100 0x20>; 69 interrupts = <0x0 0x7 0x4>; 70 interrupt-parent = <0x1>; 71 clocks = <0x2 0xc>; 72 }; 73 74 can@e0008000 { 75 compatible = "xlnx,zynq-can-1.0"; 76 status = "disabled"; 77 clocks = <0x2 0x13 0x2 0x24>; 78 clock-names = "can_clk", "pclk"; 79 reg = <0xe0008000 0x1000>; 80 interrupts = <0x0 0x1c 0x4>; 81 interrupt-parent = <0x1>; 82 tx-fifo-depth = <0x40>; 83 rx-fifo-depth = <0x40>; 84 }; 85 86 can@e0009000 { 87 compatible = "xlnx,zynq-can-1.0"; 88 status = "disabled"; 89 clocks = <0x2 0x14 0x2 0x25>; 90 clock-names = "can_clk", "pclk"; 91 reg = <0xe0009000 0x1000>; 92 interrupts = <0x0 0x33 0x4>; 93 interrupt-parent = <0x1>; 94 tx-fifo-depth = <0x40>; 95 rx-fifo-depth = <0x40>; 96 }; 97 98 gpio@e000a000 { 99 compatible = "xlnx,zynq-gpio-1.0"; 100 #gpio-cells = <0x2>; 101 clocks = <0x2 0x2a>; 102 gpio-controller; 103 interrupt-controller; 104 #interrupt-cells = <0x2>; 105 interrupt-parent = <0x1>; 106 interrupts = <0x0 0x14 0x4>; 107 reg = <0xe000a000 0x1000>; 108 linux,phandle = <0x6>; 109 phandle = <0x6>; 110 }; 111 112 i2c@e0004000 { 113 compatible = "cdns,i2c-r1p10"; 114 status = "disabled"; 115 clocks = <0x2 0x26>; 116 interrupt-parent = <0x1>; 117 interrupts = <0x0 0x19 0x4>; 118 reg = <0xe0004000 0x1000>; 119 #address-cells = <0x1>; 120 #size-cells = <0x0>; 121 }; 122 123 i2c@e0005000 { 124 compatible = "cdns,i2c-r1p10"; 125 status = "disabled"; 126 clocks = <0x2 0x27>; 127 interrupt-parent = <0x1>; 128 interrupts = <0x0 0x30 0x4>; 129 reg = <0xe0005000 0x1000>; 130 #address-cells = <0x1>; 131 #size-cells = <0x0>; 132 }; 133 134 interrupt-controller@f8f01000 { 135 compatible = "arm,cortex-a9-gic"; 136 #interrupt-cells = <0x3>; 137 interrupt-controller; 138 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 139 linux,phandle = <0x1>; 140 phandle = <0x1>; 141 }; 142 143 cache-controller@f8f02000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0xf8f02000 0x1000>; 146 interrupts = <0x0 0x2 0x4>; 147 arm,data-latency = <0x3 0x2 0x2>; 148 arm,tag-latency = <0x2 0x2 0x2>; 149 cache-unified; 150 cache-level = <0x2>; 151 }; 152 153 memory-controller@f8006000 { 154 compatible = "xlnx,zynq-ddrc-a05"; 155 reg = <0xf8006000 0x1000>; 156 }; 157 158 ocmc@f800c000 { 159 compatible = "xlnx,zynq-ocmc-1.0"; 160 interrupt-parent = <0x1>; 161 interrupts = <0x0 0x3 0x4>; 162 reg = <0xf800c000 0x1000>; 163 }; 164 165 serial@e0000000 { 166 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 167 status = "disabled"; 168 clocks = <0x2 0x17 0x2 0x28>; 169 clock-names = "uart_clk", "pclk"; 170 reg = <0xe0000000 0x1000>; 171 interrupts = <0x0 0x1b 0x4>; 172 }; 173 174 serial@e0001000 { 175 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 176 status = "okay"; 177 clocks = <0x2 0x18 0x2 0x29>; 178 clock-names = "uart_clk", "pclk"; 179 reg = <0xe0001000 0x1000>; 180 interrupts = <0x0 0x32 0x4>; 181 }; 182 183 spi@e0006000 { 184 compatible = "xlnx,zynq-spi-r1p6"; 185 reg = <0xe0006000 0x1000>; 186 status = "okay"; 187 interrupt-parent = <0x1>; 188 interrupts = <0x0 0x1a 0x4>; 189 clocks = <0x2 0x19 0x2 0x22>; 190 clock-names = "ref_clk", "pclk"; 191 #address-cells = <0x1>; 192 #size-cells = <0x0>; 193 194 ad9361-phy@0 { 195 compatible = "adi,ad9361"; 196 reg = <0x0>; 197 spi-cpha; 198 spi-max-frequency = <0x989680>; 199 clocks = <0x5 0x0>; 200 clock-names = "ad9361_ext_refclk"; 201 clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; 202 #clock-cells = <0x1>; 203 adi,digital-interface-tune-skip-mode = <0x0>; 204 adi,pp-tx-swap-enable; 205 adi,pp-rx-swap-enable; 206 adi,rx-frame-pulse-mode-enable; 207 adi,lvds-mode-enable; 208 adi,lvds-bias-mV = <0x96>; 209 adi,lvds-rx-onchip-termination-enable; 210 adi,rx-data-delay = <0x4>; 211 adi,tx-fb-clock-delay = <0x7>; 212 adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>; 213 adi,2rx-2tx-mode-enable; 214 adi,frequency-division-duplex-mode-enable; 215 adi,rx-rf-port-input-select = <0x0>; 216 adi,tx-rf-port-input-select = <0x0>; 217 adi,tx-attenuation-mdB = <0x2710>; 218 adi,tx-lo-powerdown-managed-enable; 219 adi,rf-rx-bandwidth-hz = <0x112a880>; 220 adi,rf-tx-bandwidth-hz = <0x112a880>; 221 adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; 222 adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; 223 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 224 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 225 adi,gc-rx1-mode = <0x2>; 226 adi,gc-rx2-mode = <0x2>; 227 adi,gc-adc-ovr-sample-size = <0x4>; 228 adi,gc-adc-small-overload-thresh = <0x2f>; 229 adi,gc-adc-large-overload-thresh = <0x3a>; 230 adi,gc-lmt-overload-high-thresh = <0x320>; 231 adi,gc-lmt-overload-low-thresh = <0x2c0>; 232 adi,gc-dec-pow-measurement-duration = <0x2000>; 233 adi,gc-low-power-thresh = <0x18>; 234 adi,mgc-inc-gain-step = <0x2>; 235 adi,mgc-dec-gain-step = <0x2>; 236 adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; 237 adi,agc-attack-delay-extra-margin-us = <0x1>; 238 adi,agc-outer-thresh-high = <0x5>; 239 adi,agc-outer-thresh-high-dec-steps = <0x2>; 240 adi,agc-inner-thresh-high = <0xa>; 241 adi,agc-inner-thresh-high-dec-steps = <0x1>; 242 adi,agc-inner-thresh-low = <0xc>; 243 adi,agc-inner-thresh-low-inc-steps = <0x1>; 244 adi,agc-outer-thresh-low = <0x12>; 245 adi,agc-outer-thresh-low-inc-steps = <0x2>; 246 adi,agc-adc-small-overload-exceed-counter = <0xa>; 247 adi,agc-adc-large-overload-exceed-counter = <0xa>; 248 adi,agc-adc-large-overload-inc-steps = <0x2>; 249 adi,agc-lmt-overload-large-exceed-counter = <0xa>; 250 adi,agc-lmt-overload-small-exceed-counter = <0xa>; 251 adi,agc-lmt-overload-large-inc-steps = <0x2>; 252 adi,agc-gain-update-interval-us = <0x3e8>; 253 adi,fagc-dec-pow-measurement-duration = <0x40>; 254 adi,fagc-lp-thresh-increment-steps = <0x1>; 255 adi,fagc-lp-thresh-increment-time = <0x5>; 256 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; 257 adi,fagc-final-overrange-count = <0x3>; 258 adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; 259 adi,fagc-lmt-final-settling-steps = <0x1>; 260 adi,fagc-lock-level = <0xa>; 261 adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; 262 adi,fagc-lock-level-lmt-gain-increase-enable; 263 adi,fagc-lpf-final-settling-steps = <0x1>; 264 adi,fagc-optimized-gain-offset = <0x5>; 265 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 266 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 267 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; 268 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 269 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; 270 adi,fagc-rst-gla-large-adc-overload-enable; 271 adi,fagc-rst-gla-large-lmt-overload-enable; 272 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; 273 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 274 adi,fagc-state-wait-time-ns = <0x104>; 275 adi,fagc-use-last-lock-level-for-set-gain-enable; 276 adi,rssi-restart-mode = <0x3>; 277 adi,rssi-delay = <0x1>; 278 adi,rssi-wait = <0x1>; 279 adi,rssi-duration = <0x3e8>; 280 adi,ctrl-outs-index = <0x0>; 281 adi,ctrl-outs-enable-mask = <0xff>; 282 adi,temp-sense-measurement-interval-ms = <0x3e8>; 283 adi,temp-sense-offset-signed = <0xce>; 284 adi,temp-sense-periodic-measurement-enable; 285 adi,aux-dac-manual-mode-enable; 286 adi,aux-dac1-default-value-mV = <0x0>; 287 adi,aux-dac1-rx-delay-us = <0x0>; 288 adi,aux-dac1-tx-delay-us = <0x0>; 289 adi,aux-dac2-default-value-mV = <0x0>; 290 adi,aux-dac2-rx-delay-us = <0x0>; 291 adi,aux-dac2-tx-delay-us = <0x0>; 292 en_agc-gpios = <0x6 0x62 0x0>; 293 sync-gpios = <0x6 0x63 0x0>; 294 reset-gpios = <0x6 0x64 0x0>; 295 enable-gpios = <0x6 0x65 0x0>; 296 txnrx-gpios = <0x6 0x66 0x0>; 297 linux,phandle = <0x11>; 298 phandle = <0x11>; 299 }; 300 }; 301 302 spi@e0007000 { 303 compatible = "xlnx,zynq-spi-r1p6"; 304 reg = <0xe0007000 0x1000>; 305 status = "okay"; 306 interrupt-parent = <0x1>; 307 interrupts = <0x0 0x31 0x4>; 308 clocks = <0x2 0x1a 0x2 0x23>; 309 clock-names = "ref_clk", "pclk"; 310 #address-cells = <0x1>; 311 #size-cells = <0x0>; 312 313 adf4351-udc-tx-pmod@0 { 314 compatible = "adi,adf4351"; 315 reg = <0x0>; 316 spi-max-frequency = <0x989680>; 317 clocks = <0x7>; 318 clock-names = "clkin"; 319 adi,channel-spacing = <0xf4240>; 320 adi,power-up-frequency = <0x160dc080>; 321 adi,phase-detector-polarity-positive-enable; 322 adi,charge-pump-current = <0x9c4>; 323 adi,output-power = <0x3>; 324 adi,mute-till-lock-enable; 325 adi,muxout-select = <0x6>; 326 gpios = <0x6 0x68 0x0>; 327 }; 328 329 adf4351-udc-rx-pmod@1 { 330 compatible = "adi,adf4351"; 331 reg = <0x1>; 332 spi-max-frequency = <0x989680>; 333 clocks = <0x7>; 334 clock-names = "clkin"; 335 adi,channel-spacing = <0xf4240>; 336 adi,power-up-frequency = <0x1443fd00>; 337 adi,phase-detector-polarity-positive-enable; 338 adi,charge-pump-current = <0x9c4>; 339 adi,output-power = <0x3>; 340 adi,mute-till-lock-enable; 341 adi,muxout-select = <0x6>; 342 gpios = <0x6 0x67 0x0>; 343 }; 344 }; 345 346 spi@e000d000 { 347 clock-names = "ref_clk", "pclk"; 348 clocks = <0x2 0xa 0x2 0x2b>; 349 compatible = "xlnx,zynq-qspi-1.0"; 350 status = "okay"; 351 interrupt-parent = <0x1>; 352 interrupts = <0x0 0x13 0x4>; 353 reg = <0xe000d000 0x1000>; 354 #address-cells = <0x1>; 355 #size-cells = <0x0>; 356 is-dual = <0x0>; 357 num-cs = <0x1>; 358 359 ps7-qspi@0 { 360 #address-cells = <0x1>; 361 #size-cells = <0x1>; 362 compatible = "n25q128a11"; 363 reg = <0x0>; 364 spi-tx-bus-width = <0x1>; 365 spi-rx-bus-width = <0x4>; 366 367 partition@0 { 368 label = "boot"; 369 reg = <0x0 0x500000>; 370 }; 371 372 partition@500000 { 373 label = "bootenv"; 374 reg = <0x500000 0x20000>; 375 }; 376 377 partition@520000 { 378 label = "config"; 379 reg = <0x520000 0x20000>; 380 }; 381 382 partition@540000 { 383 label = "image"; 384 reg = <0x540000 0xa80000>; 385 }; 386 387 partition@fc0000 { 388 label = "spare"; 389 reg = <0xfc0000 0x0>; 390 }; 391 }; 392 }; 393 394 memory-controller@e000e000 { 395 #address-cells = <0x1>; 396 #size-cells = <0x1>; 397 status = "disabled"; 398 clock-names = "memclk", "aclk"; 399 clocks = <0x2 0xb 0x2 0x2c>; 400 compatible = "arm,pl353-smc-r2p1"; 401 interrupt-parent = <0x1>; 402 interrupts = <0x0 0x12 0x4>; 403 ranges; 404 reg = <0xe000e000 0x1000>; 405 406 flash@e1000000 { 407 status = "disabled"; 408 compatible = "arm,pl353-nand-r2p1"; 409 reg = <0xe1000000 0x1000000>; 410 #address-cells = <0x1>; 411 #size-cells = <0x1>; 412 }; 413 414 flash@e2000000 { 415 status = "disabled"; 416 compatible = "cfi-flash"; 417 reg = <0xe2000000 0x2000000>; 418 #address-cells = <0x1>; 419 #size-cells = <0x1>; 420 }; 421 }; 422 423 ethernet@e000b000 { 424 compatible = "cdns,zynq-gem", "cdns,gem"; 425 reg = <0xe000b000 0x1000>; 426 status = "okay"; 427 interrupts = <0x0 0x16 0x4>; 428 clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; 429 clock-names = "pclk", "hclk", "tx_clk"; 430 #address-cells = <0x1>; 431 #size-cells = <0x0>; 432 phy-handle = <0x8>; 433 phy-mode = "rgmii-id"; 434 435 phy@7 { 436 device_type = "ethernet-phy"; 437 reg = <0x7>; 438 linux,phandle = <0x8>; 439 phandle = <0x8>; 440 }; 441 }; 442 443 ethernet@e000c000 { 444 compatible = "cdns,zynq-gem", "cdns,gem"; 445 reg = <0xe000c000 0x1000>; 446 status = "disabled"; 447 interrupts = <0x0 0x2d 0x4>; 448 clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; 449 clock-names = "pclk", "hclk", "tx_clk"; 450 #address-cells = <0x1>; 451 #size-cells = <0x0>; 452 }; 453 454 mmc@e0100000 { 455 compatible = "arasan,sdhci-8.9a"; 456 status = "okay"; 457 clock-names = "clk_xin", "clk_ahb"; 458 clocks = <0x2 0x15 0x2 0x20>; 459 interrupt-parent = <0x1>; 460 interrupts = <0x0 0x18 0x4>; 461 reg = <0xe0100000 0x1000>; 462 }; 463 464 mmc@e0101000 { 465 compatible = "arasan,sdhci-8.9a"; 466 status = "disabled"; 467 clock-names = "clk_xin", "clk_ahb"; 468 clocks = <0x2 0x16 0x2 0x21>; 469 interrupt-parent = <0x1>; 470 interrupts = <0x0 0x2f 0x4>; 471 reg = <0xe0101000 0x1000>; 472 }; 473 474 slcr@f8000000 { 475 u-boot,dm-pre-reloc; 476 #address-cells = <0x1>; 477 #size-cells = <0x1>; 478 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 479 reg = <0xf8000000 0x1000>; 480 ranges; 481 linux,phandle = <0x9>; 482 phandle = <0x9>; 483 484 clkc@100 { 485 u-boot,dm-pre-reloc; 486 #clock-cells = <0x1>; 487 compatible = "xlnx,ps7-clkc"; 488 fclk-enable = <0xf>; 489 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; 490 reg = <0x100 0x100>; 491 ps-clk-frequency = <0x1fca055>; 492 linux,phandle = <0x2>; 493 phandle = <0x2>; 494 }; 495 496 rstc@200 { 497 compatible = "xlnx,zynq-reset"; 498 reg = <0x200 0x48>; 499 #reset-cells = <0x1>; 500 syscon = <0x9>; 501 }; 502 503 pinctrl@700 { 504 compatible = "xlnx,pinctrl-zynq"; 505 reg = <0x700 0x200>; 506 syscon = <0x9>; 507 }; 508 }; 509 510 dmac@f8003000 { 511 compatible = "arm,pl330", "arm,primecell"; 512 reg = <0xf8003000 0x1000>; 513 interrupt-parent = <0x1>; 514 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; 515 interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; 516 #dma-cells = <0x1>; 517 #dma-channels = <0x8>; 518 #dma-requests = <0x4>; 519 clocks = <0x2 0x1b>; 520 clock-names = "apb_pclk"; 521 linux,phandle = <0xe>; 522 phandle = <0xe>; 523 }; 524 525 devcfg@f8007000 { 526 compatible = "xlnx,zynq-devcfg-1.0"; 527 interrupt-parent = <0x1>; 528 interrupts = <0x0 0x8 0x4>; 529 reg = <0xf8007000 0x100>; 530 clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; 531 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 532 syscon = <0x9>; 533 linux,phandle = <0x4>; 534 phandle = <0x4>; 535 }; 536 537 efuse@f800d000 { 538 compatible = "xlnx,zynq-efuse"; 539 reg = <0xf800d000 0x20>; 540 }; 541 542 timer@f8f00200 { 543 compatible = "arm,cortex-a9-global-timer"; 544 reg = <0xf8f00200 0x20>; 545 interrupts = <0x1 0xb 0x301>; 546 interrupt-parent = <0x1>; 547 clocks = <0x2 0x4>; 548 }; 549 550 timer@f8001000 { 551 interrupt-parent = <0x1>; 552 interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; 553 compatible = "cdns,ttc"; 554 clocks = <0x2 0x6>; 555 reg = <0xf8001000 0x1000>; 556 }; 557 558 timer@f8002000 { 559 interrupt-parent = <0x1>; 560 interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; 561 compatible = "cdns,ttc"; 562 clocks = <0x2 0x6>; 563 reg = <0xf8002000 0x1000>; 564 }; 565 566 timer@f8f00600 { 567 interrupt-parent = <0x1>; 568 interrupts = <0x1 0xd 0x301>; 569 compatible = "arm,cortex-a9-twd-timer"; 570 reg = <0xf8f00600 0x20>; 571 clocks = <0x2 0x4>; 572 }; 573 574 usb@e0002000 { 575 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 576 status = "okay"; 577 clocks = <0x2 0x1c>; 578 interrupt-parent = <0x1>; 579 interrupts = <0x0 0x15 0x4>; 580 reg = <0xe0002000 0x1000>; 581 phy_type = "ulpi"; 582 dr_mode = "host"; 583 xlnx,phy-reset-gpio = <0x6 0x7 0x0>; 584 }; 585 586 usb@e0003000 { 587 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 588 status = "disabled"; 589 clocks = <0x2 0x1d>; 590 interrupt-parent = <0x1>; 591 interrupts = <0x0 0x2c 0x4>; 592 reg = <0xe0003000 0x1000>; 593 phy_type = "ulpi"; 594 }; 595 596 watchdog@f8005000 { 597 clocks = <0x2 0x2d>; 598 compatible = "cdns,wdt-r1p2"; 599 interrupt-parent = <0x1>; 600 interrupts = <0x0 0x9 0x1>; 601 reg = <0xf8005000 0x1000>; 602 timeout-sec = <0xa>; 603 }; 604 }; 605 606 aliases { 607 ethernet0 = "/amba/ethernet@e000b000"; 608 serial0 = "/amba/serial@e0001000"; 609 }; 610 611 memory { 612 device_type = "memory"; 613 reg = <0x0 0x40000000>; 614 }; 615 616 chosen { 617 bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait"; 618 linux,stdout-path = "/amba@0/uart@E0001000"; 619 }; 620 621 leds { 622 compatible = "gpio-leds"; 623 624 ds12 { 625 label = "ds12:green"; 626 gpios = <0x6 0x8 0x0>; 627 }; 628 629 ds15 { 630 label = "ds15:green"; 631 gpios = <0x6 0x3a 0x0>; 632 }; 633 634 ds16 { 635 label = "ds16:green"; 636 gpios = <0x6 0x3b 0x0>; 637 }; 638 639 ds17 { 640 label = "ds17:green"; 641 gpios = <0x6 0x3c 0x0>; 642 }; 643 644 ds18 { 645 label = "ds18:green"; 646 gpios = <0x6 0x3d 0x0>; 647 }; 648 649 ds19 { 650 label = "ds19:green"; 651 gpios = <0x6 0x3e 0x0>; 652 }; 653 654 ds20 { 655 label = "ds20:green"; 656 gpios = <0x6 0x3f 0x0>; 657 }; 658 659 ds21 { 660 label = "ds21:green"; 661 gpios = <0x6 0x40 0x0>; 662 }; 663 664 ds22 { 665 label = "ds22:green"; 666 gpios = <0x6 0x41 0x0>; 667 }; 668 669 ds23 { 670 label = "ds23:green"; 671 gpios = <0x6 0xa 0x0>; 672 }; 673 }; 674 675 gpio_keys { 676 compatible = "gpio-keys"; 677 #address-cells = <0x1>; 678 #size-cells = <0x0>; 679 autorepeat; 680 681 sw5 { 682 label = "Left"; 683 linux,code = <0x69>; 684 gpios = <0x6 0x36 0x0>; 685 }; 686 687 sw7 { 688 label = "Right"; 689 linux,code = <0x6a>; 690 gpios = <0x6 0x37 0x0>; 691 }; 692 693 sw15_0 { 694 label = "SW15_0"; 695 linux,code = <0x0>; 696 linux,input-type = <0x5>; 697 gpios = <0x6 0x38 0x0>; 698 }; 699 700 sw15_1 { 701 label = "SW15_1"; 702 linux,code = <0x1>; 703 linux,input-type = <0x5>; 704 gpios = <0x6 0x39 0x0>; 705 }; 706 707 sw13 { 708 label = "Select"; 709 linux,code = <0x1c>; 710 gpios = <0x6 0xe 0x0>; 711 }; 712 713 sw14 { 714 label = "SW14"; 715 linux,code = <0x1>; 716 gpios = <0x6 0xc 0x0>; 717 }; 718 }; 719 720 fpga-axi@0 { 721 compatible = "simple-bus"; 722 #address-cells = <0x1>; 723 #size-cells = <0x1>; 724 ranges; 725 726 i2c@41600000 { 727 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; 728 reg = <0x41600000 0x10000>; 729 interrupt-parent = <0x1>; 730 interrupts = <0x0 0x3a 0x4>; 731 clocks = <0x2 0xf>; 732 clock-names = "pclk"; 733 #address-cells = <0x1>; 734 #size-cells = <0x0>; 735 736 mux@74 { 737 compatible = "pca9548"; 738 reg = <0x74>; 739 #address-cells = <0x1>; 740 #size-cells = <0x0>; 741 742 i2c@1 { 743 #size-cells = <0x0>; 744 #address-cells = <0x1>; 745 reg = <0x1>; 746 747 adv7511@39 { 748 compatible = "adi,adv7511"; 749 reg = <0x39 0x3f>; 750 reg-names = "primary", "edid"; 751 adi,input-depth = <0x8>; 752 adi,input-colorspace = "yuv422"; 753 adi,input-clock = "1x"; 754 adi,input-style = <0x1>; 755 adi,input-justification = "right"; 756 adi,clock-delay = <0x0>; 757 #sound-dai-cells = <0x0>; 758 linux,phandle = <0x14>; 759 phandle = <0x14>; 760 761 ports { 762 #address-cells = <0x1>; 763 #size-cells = <0x0>; 764 765 port@0 { 766 reg = <0x0>; 767 768 endpoint { 769 remote-endpoint = <0xa>; 770 linux,phandle = <0xd>; 771 phandle = <0xd>; 772 }; 773 }; 774 775 port@1 { 776 reg = <0x1>; 777 }; 778 }; 779 }; 780 }; 781 782 i2c@4 { 783 #size-cells = <0x0>; 784 #address-cells = <0x1>; 785 reg = <0x4>; 786 787 rtc@51 { 788 compatible = "rtc8564"; 789 reg = <0x51>; 790 }; 791 }; 792 793 i2c@5 { 794 #size-cells = <0x0>; 795 #address-cells = <0x1>; 796 reg = <0x5>; 797 798 ad7291@2f { 799 compatible = "adi,ad7291"; 800 reg = <0x2f>; 801 }; 802 803 eeprom@50 { 804 compatible = "at24,24c02"; 805 reg = <0x50>; 806 }; 807 }; 808 }; 809 }; 810/* 811 dma@43000000 { 812 compatible = "adi,axi-dmac-1.00.a"; 813 reg = <0x43000000 0x10000>; 814 #dma-cells = <0x1>; 815 interrupts = <0x0 0x3b 0x0>; 816 clocks = <0x2 0x10>; 817 linux,phandle = <0xb>; 818 phandle = <0xb>; 819 820 adi,channels { 821 #size-cells = <0x0>; 822 #address-cells = <0x1>; 823 824 dma-channel@0 { 825 reg = <0x0>; 826 adi,source-bus-width = <0x40>; 827 adi,source-bus-type = <0x0>; 828 adi,destination-bus-width = <0x40>; 829 adi,destination-bus-type = <0x1>; 830 }; 831 }; 832 }; 833 834 axi-clkgen@79000000 { 835 compatible = "adi,axi-clkgen-2.00.a"; 836 reg = <0x79000000 0x10000>; 837 #clock-cells = <0x0>; 838 clocks = <0x2 0x10>; 839 linux,phandle = <0xc>; 840 phandle = <0xc>; 841 }; 842 843 axi_hdmi@70e00000 { 844 compatible = "adi,axi-hdmi-tx-1.00.a"; 845 reg = <0x70e00000 0x10000>; 846 dmas = <0xb 0x0>; 847 dma-names = "video"; 848 clocks = <0xc>; 849 850 port { 851 852 endpoint { 853 remote-endpoint = <0xd>; 854 linux,phandle = <0xa>; 855 phandle = <0xa>; 856 }; 857 }; 858 }; 859 860 axi-spdif-tx@75c00000 { 861 compatible = "adi,axi-spdif-tx-1.00.a"; 862 reg = <0x75c00000 0x1000>; 863 dmas = <0xe 0x0>; 864 dma-names = "tx"; 865 clocks = <0x2 0xf 0xf>; 866 clock-names = "axi", "ref"; 867 #sound-dai-cells = <0x0>; 868 linux,phandle = <0x13>; 869 phandle = <0x13>; 870 }; 871*/ 872 /*axi-sysid-0@45000000 { 873 compatible = "adi,axi-sysid-1.00.a"; 874 reg = <0x45000000 0x10000>; 875 };*/ 876 877 // dma@7c400000 { 878 // compatible = "adi,axi-dmac-1.00.a"; 879 // reg = <0x7c400000 0x10000>; 880 // #dma-cells = <0x1>; 881 // interrupts = <0x0 0x39 0x0>; 882 // clocks = <0x2 0x10>; 883 // linux,phandle = <0x10>; 884 // phandle = <0x10>; 885 886 // adi,channels { 887 // #size-cells = <0x0>; 888 // #address-cells = <0x1>; 889 890 // dma-channel@0 { 891 // reg = <0x0>; 892 // adi,source-bus-width = <0x40>; 893 // adi,source-bus-type = <0x2>; 894 // adi,destination-bus-width = <0x40>; 895 // adi,destination-bus-type = <0x0>; 896 // }; 897 // }; 898 // }; 899 900 // dma@7c420000 { 901 // compatible = "adi,axi-dmac-1.00.a"; 902 // reg = <0x7c420000 0x10000>; 903 // #dma-cells = <0x1>; 904 // interrupts = <0x0 0x38 0x0>; 905 // clocks = <0x2 0x10>; 906 // linux,phandle = <0x12>; 907 // phandle = <0x12>; 908 909 // adi,channels { 910 // #size-cells = <0x0>; 911 // #address-cells = <0x1>; 912 913 // dma-channel@0 { 914 // reg = <0x0>; 915 // adi,source-bus-width = <0x40>; 916 // adi,source-bus-type = <0x0>; 917 // adi,destination-bus-width = <0x40>; 918 // adi,destination-bus-type = <0x2>; 919 // }; 920 // }; 921 // }; 922 923 sdr: sdr { 924 compatible ="sdr,sdr"; 925 dmas = <&rx_dma 1 926 &tx_dma 0>; 927 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 928 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 929 interrupt-parent = <1>; 930 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 931 } ; 932 933 axidmatest_1: axidmatest@1 { 934 compatible ="xlnx,axi-dma-test-1.00.a"; 935 dmas = <&rx_dma 0 936 &rx_dma 1>; 937 dma-names = "axidma0", "axidma1"; 938 } ; 939 940 tx_dma: dma@80400000 { 941 #dma-cells = <1>; 942 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 943 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 944 compatible = "xlnx,axi-dma-1.00.a"; 945 interrupt-names = "mm2s_introut", "s2mm_introut"; 946 interrupt-parent = <1>; 947 interrupts = <0 35 4 0 36 4>; 948 reg = <0x80400000 0x10000>; 949 xlnx,addrwidth = <0x20>; 950 xlnx,include-sg ; 951 xlnx,sg-length-width = <0xe>; 952 dma-channel@80400000 { 953 compatible = "xlnx,axi-dma-mm2s-channel"; 954 dma-channels = <0x1>; 955 interrupts = <0 35 4>; 956 xlnx,datawidth = <0x40>; 957 xlnx,device-id = <0x0>; 958 }; 959 dma-channel@80400030 { 960 compatible = "xlnx,axi-dma-s2mm-channel"; 961 dma-channels = <0x1>; 962 interrupts = <0 36 4>; 963 xlnx,datawidth = <0x40>; 964 xlnx,device-id = <0x0>; 965 }; 966 }; 967 968 rx_dma: dma@80410000 { 969 #dma-cells = <1>; 970 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 971 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 972 compatible = "xlnx,axi-dma-1.00.a"; 973 //dma-coherent ; 974 interrupt-names = "mm2s_introut", "s2mm_introut"; 975 interrupt-parent = <1>; 976 interrupts = <0 31 4 0 32 4>; 977 reg = <0x80410000 0x10000>; 978 xlnx,addrwidth = <0x20>; 979 xlnx,include-sg ; 980 xlnx,sg-length-width = <0xe>; 981 dma-channel@80410000 { 982 compatible = "xlnx,axi-dma-mm2s-channel"; 983 dma-channels = <0x1>; 984 interrupts = <0 31 4>; 985 xlnx,datawidth = <0x40>; 986 xlnx,device-id = <0x1>; 987 }; 988 dma-channel@80410030 { 989 compatible = "xlnx,axi-dma-s2mm-channel"; 990 dma-channels = <0x1>; 991 interrupts = <0 32 4>; 992 xlnx,datawidth = <0x40>; 993 xlnx,device-id = <0x1>; 994 }; 995 }; 996 997 tx_intf_0: tx_intf@83c00000 { 998 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 999 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 1000 compatible = "sdr,tx_intf"; 1001 interrupt-names = "tx_itrpt"; 1002 interrupt-parent = <1>; 1003 interrupts = <0 34 1>; 1004 reg = <0x83c00000 0x10000>; 1005 xlnx,s00-axi-addr-width = <0x7>; 1006 xlnx,s00-axi-data-width = <0x20>; 1007 }; 1008 1009 rx_intf_0: rx_intf@83c20000 { 1010 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 1011 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 1012 compatible = "sdr,rx_intf"; 1013 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 1014 interrupt-parent = <1>; 1015 interrupts = <0 29 1 0 30 1>; 1016 reg = <0x83c20000 0x10000>; 1017 xlnx,s00-axi-addr-width = <0x7>; 1018 xlnx,s00-axi-data-width = <0x20>; 1019 }; 1020 1021 openofdm_tx_0: openofdm_tx@83c10000 { 1022 clock-names = "clk"; 1023 clocks = <0x2 0x11>; 1024 compatible = "sdr,openofdm_tx"; 1025 reg = <0x83c10000 0x10000>; 1026 }; 1027 1028 openofdm_rx_0: openofdm_rx@83c30000 { 1029 clock-names = "clk"; 1030 clocks = <0x2 0x11>; 1031 compatible = "sdr,openofdm_rx"; 1032 reg = <0x83c30000 0x10000>; 1033 }; 1034 1035 xpu_0: xpu@83c40000 { 1036 clock-names = "s00_axi_aclk"; 1037 clocks = <0x2 0x11>; 1038 compatible = "sdr,xpu"; 1039 reg = <0x83c40000 0x10000>; 1040 }; 1041 1042 side_ch_0: side_ch@83c50000 { 1043 clock-names = "s00_axi_aclk"; 1044 clocks = <0x2 0x11>; 1045 compatible = "sdr,side_ch"; 1046 reg = <0x83c50000 0x10000>; 1047 dmas = <&rx_dma 0 1048 &tx_dma 1>; 1049 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 1050 }; 1051 1052 cf-ad9361-lpc@79020000 { 1053 compatible = "adi,axi-ad9361-6.00.a"; 1054 reg = <0x79020000 0x6000>; 1055 // dmas = <0x10 0x0>; 1056 // dma-names = "rx"; 1057 spibus-connected = <0x11>; 1058 }; 1059 1060 cf-ad9361-dds-core-lpc@79024000 { 1061 compatible = "adi,axi-ad9361-dds-6.00.a"; 1062 reg = <0x79024000 0x1000>; 1063 clocks = <0x11 0xd>; 1064 clock-names = "sampl_clk"; 1065 // dmas = <0x12 0x0>; 1066 // dma-names = "tx"; 1067 }; 1068 }; 1069/* 1070 audio_clock { 1071 compatible = "fixed-clock"; 1072 #clock-cells = <0x0>; 1073 clock-frequency = <0xbb8000>; 1074 linux,phandle = <0xf>; 1075 phandle = <0xf>; 1076 }; 1077 1078 adv7511_hdmi_snd { 1079 compatible = "simple-audio-card"; 1080 simple-audio-card,name = "HDMI monitor"; 1081 simple-audio-card,widgets = "Speaker", "Speaker"; 1082 simple-audio-card,routing = "Speaker", "TX"; 1083 1084 simple-audio-card,dai-link@0 { 1085 format = "spdif"; 1086 1087 cpu { 1088 sound-dai = <0x13>; 1089 frame-master; 1090 bitclock-master; 1091 }; 1092 1093 codec { 1094 sound-dai = <0x14>; 1095 }; 1096 }; 1097 }; 1098*/ 1099 clocks { 1100 1101 clock@0 { 1102 compatible = "fixed-clock"; 1103 clock-frequency = <0x2625a00>; 1104 clock-output-names = "ad9361_ext_refclk"; 1105 #clock-cells = <0x0>; 1106 linux,phandle = <0x5>; 1107 phandle = <0x5>; 1108 }; 1109 1110 clock@1 { 1111 compatible = "fixed-clock"; 1112 clock-frequency = <0x17d7840>; 1113 clock-output-names = "refclk"; 1114 #clock-cells = <0x0>; 1115 linux,phandle = <0x7>; 1116 phandle = <0x7>; 1117 }; 1118 }; 1119}; 1120