1/dts-v1/; 2 3/ { 4 #address-cells = <0x01>; 5 #size-cells = <0x01>; 6 compatible = "xlnx,zynq-7000"; 7 interrupt-parent = <0x01>; 8 model = "Xilinx Zynq ZC702"; 9 10 cpus { 11 #address-cells = <0x01>; 12 #size-cells = <0x00>; 13 14 cpu@0 { 15 compatible = "arm,cortex-a9"; 16 device_type = "cpu"; 17 reg = <0x00>; 18 clocks = <0x02 0x03>; 19 clock-latency = <0x3e8>; 20 cpu0-supply = <0x03>; 21 operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; 22 phandle = <0x12>; 23 }; 24 25 cpu@1 { 26 compatible = "arm,cortex-a9"; 27 device_type = "cpu"; 28 reg = <0x01>; 29 clocks = <0x02 0x03>; 30 phandle = <0x14>; 31 }; 32 }; 33 34 fpga-full { 35 compatible = "fpga-region"; 36 fpga-mgr = <0x04>; 37 #address-cells = <0x01>; 38 #size-cells = <0x01>; 39 ranges; 40 phandle = <0x21>; 41 }; 42 43 pmu@f8891000 { 44 compatible = "arm,cortex-a9-pmu"; 45 interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; 46 interrupt-parent = <0x01>; 47 reg = <0xf8891000 0x1000 0xf8893000 0x1000>; 48 }; 49 50 fixedregulator { 51 compatible = "regulator-fixed"; 52 regulator-name = "VCCPINT"; 53 regulator-min-microvolt = <0xf4240>; 54 regulator-max-microvolt = <0xf4240>; 55 regulator-boot-on; 56 regulator-always-on; 57 phandle = <0x03>; 58 }; 59 60 replicator { 61 compatible = "arm,coresight-static-replicator"; 62 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 63 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 64 65 out-ports { 66 #address-cells = <0x01>; 67 #size-cells = <0x00>; 68 69 port@0 { 70 reg = <0x00>; 71 72 endpoint { 73 remote-endpoint = <0x05>; 74 phandle = <0x0e>; 75 }; 76 }; 77 78 port@1 { 79 reg = <0x01>; 80 81 endpoint { 82 remote-endpoint = <0x06>; 83 phandle = <0x0d>; 84 }; 85 }; 86 }; 87 88 in-ports { 89 90 port { 91 92 endpoint { 93 remote-endpoint = <0x07>; 94 phandle = <0x0f>; 95 }; 96 }; 97 }; 98 }; 99 100 axi { 101 u-boot,dm-pre-reloc; 102 compatible = "simple-bus"; 103 #address-cells = <0x01>; 104 #size-cells = <0x01>; 105 interrupt-parent = <0x01>; 106 ranges; 107 phandle = <0x22>; 108 109 adc@f8007100 { 110 compatible = "xlnx,zynq-xadc-1.00.a"; 111 reg = <0xf8007100 0x20>; 112 interrupts = <0x00 0x07 0x04>; 113 interrupt-parent = <0x01>; 114 clocks = <0x02 0x0c>; 115 phandle = <0x23>; 116 }; 117 118 can@e0008000 { 119 compatible = "xlnx,zynq-can-1.0"; 120 status = "disabled"; 121 clocks = <0x02 0x13 0x02 0x24>; 122 clock-names = "can_clk\0pclk"; 123 reg = <0xe0008000 0x1000>; 124 interrupts = <0x00 0x1c 0x04>; 125 interrupt-parent = <0x01>; 126 tx-fifo-depth = <0x40>; 127 rx-fifo-depth = <0x40>; 128 phandle = <0x24>; 129 }; 130 131 can@e0009000 { 132 compatible = "xlnx,zynq-can-1.0"; 133 status = "disabled"; 134 clocks = <0x02 0x14 0x02 0x25>; 135 clock-names = "can_clk\0pclk"; 136 reg = <0xe0009000 0x1000>; 137 interrupts = <0x00 0x33 0x04>; 138 interrupt-parent = <0x01>; 139 tx-fifo-depth = <0x40>; 140 rx-fifo-depth = <0x40>; 141 phandle = <0x25>; 142 }; 143 144 gpio@e000a000 { 145 compatible = "xlnx,zynq-gpio-1.0"; 146 #gpio-cells = <0x02>; 147 clocks = <0x02 0x2a>; 148 gpio-controller; 149 interrupt-controller; 150 #interrupt-cells = <0x02>; 151 interrupt-parent = <0x01>; 152 interrupts = <0x00 0x14 0x04>; 153 reg = <0xe000a000 0x1000>; 154 phandle = <0x09>; 155 }; 156 157 i2c@e0004000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <0x02 0x26>; 161 interrupt-parent = <0x01>; 162 interrupts = <0x00 0x19 0x04>; 163 reg = <0xe0004000 0x1000>; 164 #address-cells = <0x01>; 165 #size-cells = <0x00>; 166 phandle = <0x26>; 167 }; 168 169 i2c@e0005000 { 170 compatible = "cdns,i2c-r1p10"; 171 status = "disabled"; 172 clocks = <0x02 0x27>; 173 interrupt-parent = <0x01>; 174 interrupts = <0x00 0x30 0x04>; 175 reg = <0xe0005000 0x1000>; 176 #address-cells = <0x01>; 177 #size-cells = <0x00>; 178 phandle = <0x27>; 179 }; 180 181 interrupt-controller@f8f01000 { 182 compatible = "arm,cortex-a9-gic"; 183 #interrupt-cells = <0x03>; 184 interrupt-controller; 185 reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; 186 phandle = <0x01>; 187 }; 188 189 cache-controller@f8f02000 { 190 compatible = "arm,pl310-cache"; 191 reg = <0xf8f02000 0x1000>; 192 interrupts = <0x00 0x02 0x04>; 193 arm,data-latency = <0x03 0x02 0x02>; 194 arm,tag-latency = <0x02 0x02 0x02>; 195 cache-unified; 196 cache-level = <0x02>; 197 phandle = <0x28>; 198 }; 199 200 memory-controller@f8006000 { 201 compatible = "xlnx,zynq-ddrc-a05"; 202 reg = <0xf8006000 0x1000>; 203 phandle = <0x29>; 204 }; 205 206 ocmc@f800c000 { 207 compatible = "xlnx,zynq-ocmc-1.0"; 208 interrupt-parent = <0x01>; 209 interrupts = <0x00 0x03 0x04>; 210 reg = <0xf800c000 0x1000>; 211 phandle = <0x2a>; 212 }; 213 214 serial@e0000000 { 215 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 216 status = "disabled"; 217 clocks = <0x02 0x17 0x02 0x28>; 218 clock-names = "uart_clk\0pclk"; 219 reg = <0xe0000000 0x1000>; 220 interrupts = <0x00 0x1b 0x04>; 221 phandle = <0x2b>; 222 }; 223 224 serial@e0001000 { 225 compatible = "xlnx,xuartps\0cdns,uart-r1p8"; 226 status = "okay"; 227 clocks = <0x02 0x18 0x02 0x29>; 228 clock-names = "uart_clk\0pclk"; 229 reg = <0xe0001000 0x1000>; 230 interrupts = <0x00 0x32 0x04>; 231 phandle = <0x2c>; 232 }; 233 234 spi@e0006000 { 235 compatible = "xlnx,zynq-spi-r1p6"; 236 reg = <0xe0006000 0x1000>; 237 status = "okay"; 238 interrupt-parent = <0x01>; 239 interrupts = <0x00 0x1a 0x04>; 240 clocks = <0x02 0x19 0x02 0x22>; 241 clock-names = "ref_clk\0pclk"; 242 #address-cells = <0x01>; 243 #size-cells = <0x00>; 244 phandle = <0x2d>; 245 246 ad9361-phy@0 { 247 compatible = "adi,ad9361"; 248 reg = <0x00>; 249 spi-cpha; 250 spi-max-frequency = <0x989680>; 251 clocks = <0x08 0x00>; 252 clock-names = "ad9361_ext_refclk"; 253 clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; 254 #clock-cells = <0x01>; 255 adi,digital-interface-tune-skip-mode = <0x00>; 256 adi,pp-tx-swap-enable; 257 adi,pp-rx-swap-enable; 258 adi,rx-frame-pulse-mode-enable; 259 adi,lvds-mode-enable; 260 adi,lvds-bias-mV = <0x96>; 261 adi,lvds-rx-onchip-termination-enable; 262 adi,rx-data-delay = <0x04>; 263 adi,tx-fb-clock-delay = <0x07>; 264 adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>; 265 adi,2rx-2tx-mode-enable; 266 adi,frequency-division-duplex-mode-enable; 267 adi,rx-rf-port-input-select = <0x00>; 268 adi,tx-rf-port-input-select = <0x00>; 269 adi,tx-attenuation-mdB = <0x2710>; 270 adi,tx-lo-powerdown-managed-enable; 271 adi,rf-rx-bandwidth-hz = <0x112a880>; 272 adi,rf-tx-bandwidth-hz = <0x112a880>; 273 adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; 274 adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; 275 adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 276 adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; 277 adi,gc-rx1-mode = <0x02>; 278 adi,gc-rx2-mode = <0x02>; 279 adi,gc-adc-ovr-sample-size = <0x04>; 280 adi,gc-adc-small-overload-thresh = <0x2f>; 281 adi,gc-adc-large-overload-thresh = <0x3a>; 282 adi,gc-lmt-overload-high-thresh = <0x320>; 283 adi,gc-lmt-overload-low-thresh = <0x2c0>; 284 adi,gc-dec-pow-measurement-duration = <0x2000>; 285 adi,gc-low-power-thresh = <0x18>; 286 adi,mgc-inc-gain-step = <0x02>; 287 adi,mgc-dec-gain-step = <0x02>; 288 adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; 289 adi,agc-attack-delay-extra-margin-us = <0x01>; 290 adi,agc-outer-thresh-high = <0x05>; 291 adi,agc-outer-thresh-high-dec-steps = <0x02>; 292 adi,agc-inner-thresh-high = <0x0a>; 293 adi,agc-inner-thresh-high-dec-steps = <0x01>; 294 adi,agc-inner-thresh-low = <0x0c>; 295 adi,agc-inner-thresh-low-inc-steps = <0x01>; 296 adi,agc-outer-thresh-low = <0x12>; 297 adi,agc-outer-thresh-low-inc-steps = <0x02>; 298 adi,agc-adc-small-overload-exceed-counter = <0x0a>; 299 adi,agc-adc-large-overload-exceed-counter = <0x0a>; 300 adi,agc-adc-large-overload-inc-steps = <0x02>; 301 adi,agc-lmt-overload-large-exceed-counter = <0x0a>; 302 adi,agc-lmt-overload-small-exceed-counter = <0x0a>; 303 adi,agc-lmt-overload-large-inc-steps = <0x02>; 304 adi,agc-gain-update-interval-us = <0x3e8>; 305 adi,fagc-dec-pow-measurement-duration = <0x40>; 306 adi,fagc-lp-thresh-increment-steps = <0x01>; 307 adi,fagc-lp-thresh-increment-time = <0x05>; 308 adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; 309 adi,fagc-final-overrange-count = <0x03>; 310 adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; 311 adi,fagc-lmt-final-settling-steps = <0x01>; 312 adi,fagc-lock-level = <0x0a>; 313 adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; 314 adi,fagc-lock-level-lmt-gain-increase-enable; 315 adi,fagc-lpf-final-settling-steps = <0x01>; 316 adi,fagc-optimized-gain-offset = <0x05>; 317 adi,fagc-power-measurement-duration-in-state5 = <0x40>; 318 adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; 319 adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; 320 adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; 321 adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; 322 adi,fagc-rst-gla-large-adc-overload-enable; 323 adi,fagc-rst-gla-large-lmt-overload-enable; 324 adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; 325 adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; 326 adi,fagc-state-wait-time-ns = <0x104>; 327 adi,fagc-use-last-lock-level-for-set-gain-enable; 328 adi,rssi-restart-mode = <0x03>; 329 adi,rssi-delay = <0x01>; 330 adi,rssi-wait = <0x01>; 331 adi,rssi-duration = <0x3e8>; 332 adi,ctrl-outs-index = <0x00>; 333 adi,ctrl-outs-enable-mask = <0xff>; 334 adi,temp-sense-measurement-interval-ms = <0x3e8>; 335 adi,temp-sense-offset-signed = <0xce>; 336 adi,temp-sense-periodic-measurement-enable; 337 adi,aux-dac-manual-mode-enable; 338 adi,aux-dac1-default-value-mV = <0x00>; 339 adi,aux-dac1-rx-delay-us = <0x00>; 340 adi,aux-dac1-tx-delay-us = <0x00>; 341 adi,aux-dac2-default-value-mV = <0x00>; 342 adi,aux-dac2-rx-delay-us = <0x00>; 343 adi,aux-dac2-tx-delay-us = <0x00>; 344 en_agc-gpios = <0x09 0x62 0x00>; 345 sync-gpios = <0x09 0x63 0x00>; 346 reset-gpios = <0x09 0x64 0x00>; 347 enable-gpios = <0x09 0x65 0x00>; 348 txnrx-gpios = <0x09 0x66 0x00>; 349 phandle = <0x1d>; 350 }; 351 }; 352 353 spi@e0007000 { 354 compatible = "xlnx,zynq-spi-r1p6"; 355 reg = <0xe0007000 0x1000>; 356 status = "okay"; 357 interrupt-parent = <0x01>; 358 interrupts = <0x00 0x31 0x04>; 359 clocks = <0x02 0x1a 0x02 0x23>; 360 clock-names = "ref_clk\0pclk"; 361 #address-cells = <0x01>; 362 #size-cells = <0x00>; 363 phandle = <0x2e>; 364 365 adf4351-udc-tx-pmod@0 { 366 compatible = "adi,adf4351"; 367 reg = <0x00>; 368 spi-max-frequency = <0x989680>; 369 clocks = <0x0a>; 370 clock-names = "clkin"; 371 adi,channel-spacing = <0xf4240>; 372 adi,power-up-frequency = <0x160dc080>; 373 adi,phase-detector-polarity-positive-enable; 374 adi,charge-pump-current = <0x9c4>; 375 adi,output-power = <0x03>; 376 adi,mute-till-lock-enable; 377 adi,muxout-select = <0x06>; 378 gpios = <0x09 0x68 0x00>; 379 phandle = <0x2f>; 380 }; 381 382 adf4351-udc-rx-pmod@1 { 383 compatible = "adi,adf4351"; 384 reg = <0x01>; 385 spi-max-frequency = <0x989680>; 386 clocks = <0x0a>; 387 clock-names = "clkin"; 388 adi,channel-spacing = <0xf4240>; 389 adi,power-up-frequency = <0x1443fd00>; 390 adi,phase-detector-polarity-positive-enable; 391 adi,charge-pump-current = <0x9c4>; 392 adi,output-power = <0x03>; 393 adi,mute-till-lock-enable; 394 adi,muxout-select = <0x06>; 395 gpios = <0x09 0x67 0x00>; 396 phandle = <0x30>; 397 }; 398 }; 399 400 spi@e000d000 { 401 clock-names = "ref_clk\0pclk"; 402 clocks = <0x02 0x0a 0x02 0x2b>; 403 compatible = "xlnx,zynq-qspi-1.0"; 404 status = "okay"; 405 interrupt-parent = <0x01>; 406 interrupts = <0x00 0x13 0x04>; 407 reg = <0xe000d000 0x1000>; 408 #address-cells = <0x01>; 409 #size-cells = <0x00>; 410 is-dual = <0x00>; 411 num-cs = <0x01>; 412 phandle = <0x31>; 413 414 ps7-qspi@0 { 415 #address-cells = <0x01>; 416 #size-cells = <0x01>; 417 compatible = "n25q128a11"; 418 reg = <0x00>; 419 spi-tx-bus-width = <0x01>; 420 spi-rx-bus-width = <0x04>; 421 spi-max-frequency = <0x2faf080>; 422 phandle = <0x32>; 423 424 partition@0 { 425 label = "boot"; 426 reg = <0x00 0x500000>; 427 }; 428 429 partition@500000 { 430 label = "bootenv"; 431 reg = <0x500000 0x20000>; 432 }; 433 434 partition@520000 { 435 label = "config"; 436 reg = <0x520000 0x20000>; 437 }; 438 439 partition@540000 { 440 label = "image"; 441 reg = <0x540000 0xa80000>; 442 }; 443 444 partition@fc0000 { 445 label = "spare"; 446 reg = <0xfc0000 0x00>; 447 }; 448 }; 449 }; 450 451 memory-controller@e000e000 { 452 #address-cells = <0x01>; 453 #size-cells = <0x01>; 454 status = "disabled"; 455 clock-names = "memclk\0apb_pclk"; 456 clocks = <0x02 0x0b 0x02 0x2c>; 457 compatible = "arm,pl353-smc-r2p1\0arm,primecell"; 458 interrupt-parent = <0x01>; 459 interrupts = <0x00 0x12 0x04>; 460 ranges; 461 reg = <0xe000e000 0x1000>; 462 phandle = <0x33>; 463 464 flash@e1000000 { 465 status = "disabled"; 466 compatible = "arm,pl353-nand-r2p1"; 467 reg = <0xe1000000 0x1000000>; 468 #address-cells = <0x01>; 469 #size-cells = <0x01>; 470 phandle = <0x34>; 471 }; 472 473 flash@e2000000 { 474 status = "disabled"; 475 compatible = "cfi-flash"; 476 reg = <0xe2000000 0x2000000>; 477 #address-cells = <0x01>; 478 #size-cells = <0x01>; 479 phandle = <0x35>; 480 }; 481 }; 482 483 ethernet@e000b000 { 484 compatible = "cdns,zynq-gem\0cdns,gem"; 485 reg = <0xe000b000 0x1000>; 486 status = "okay"; 487 interrupts = <0x00 0x16 0x04>; 488 clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; 489 clock-names = "pclk\0hclk\0tx_clk"; 490 #address-cells = <0x01>; 491 #size-cells = <0x00>; 492 phy-handle = <0x0b>; 493 phy-mode = "rgmii-id"; 494 phandle = <0x36>; 495 496 phy@7 { 497 device_type = "ethernet-phy"; 498 reg = <0x07>; 499 phandle = <0x0b>; 500 }; 501 }; 502 503 ethernet@e000c000 { 504 compatible = "cdns,zynq-gem\0cdns,gem"; 505 reg = <0xe000c000 0x1000>; 506 status = "disabled"; 507 interrupts = <0x00 0x2d 0x04>; 508 clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; 509 clock-names = "pclk\0hclk\0tx_clk"; 510 #address-cells = <0x01>; 511 #size-cells = <0x00>; 512 phandle = <0x37>; 513 }; 514 515 mmc@e0100000 { 516 compatible = "arasan,sdhci-8.9a"; 517 status = "okay"; 518 clock-names = "clk_xin\0clk_ahb"; 519 clocks = <0x02 0x15 0x02 0x20>; 520 interrupt-parent = <0x01>; 521 interrupts = <0x00 0x18 0x04>; 522 reg = <0xe0100000 0x1000>; 523 phandle = <0x38>; 524 }; 525 526 mmc@e0101000 { 527 compatible = "arasan,sdhci-8.9a"; 528 status = "disabled"; 529 clock-names = "clk_xin\0clk_ahb"; 530 clocks = <0x02 0x16 0x02 0x21>; 531 interrupt-parent = <0x01>; 532 interrupts = <0x00 0x2f 0x04>; 533 reg = <0xe0101000 0x1000>; 534 phandle = <0x39>; 535 }; 536 537 slcr@f8000000 { 538 u-boot,dm-pre-reloc; 539 #address-cells = <0x01>; 540 #size-cells = <0x01>; 541 compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; 542 reg = <0xf8000000 0x1000>; 543 ranges; 544 phandle = <0x0c>; 545 546 clkc@100 { 547 u-boot,dm-pre-reloc; 548 #clock-cells = <0x01>; 549 compatible = "xlnx,ps7-clkc"; 550 fclk-enable = <0x0f>; 551 clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; 552 reg = <0x100 0x100>; 553 ps-clk-frequency = <0x1fca055>; 554 phandle = <0x02>; 555 }; 556 557 rstc@200 { 558 compatible = "xlnx,zynq-reset"; 559 reg = <0x200 0x48>; 560 #reset-cells = <0x01>; 561 syscon = <0x0c>; 562 phandle = <0x3a>; 563 }; 564 565 pinctrl@700 { 566 compatible = "xlnx,pinctrl-zynq"; 567 reg = <0x700 0x200>; 568 syscon = <0x0c>; 569 phandle = <0x3b>; 570 }; 571 }; 572 573 dmac@f8003000 { 574 compatible = "arm,pl330\0arm,primecell"; 575 reg = <0xf8003000 0x1000>; 576 interrupt-parent = <0x01>; 577 interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; 578 interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; 579 #dma-cells = <0x01>; 580 #dma-channels = <0x08>; 581 #dma-requests = <0x04>; 582 clocks = <0x02 0x1b>; 583 clock-names = "apb_pclk"; 584 phandle = <0x1a>; 585 }; 586 587 devcfg@f8007000 { 588 compatible = "xlnx,zynq-devcfg-1.0"; 589 interrupt-parent = <0x01>; 590 interrupts = <0x00 0x08 0x04>; 591 reg = <0xf8007000 0x100>; 592 clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; 593 clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; 594 syscon = <0x0c>; 595 phandle = <0x04>; 596 }; 597 598 efuse@f800d000 { 599 compatible = "xlnx,zynq-efuse"; 600 reg = <0xf800d000 0x20>; 601 phandle = <0x3c>; 602 }; 603 604 timer@f8f00200 { 605 compatible = "arm,cortex-a9-global-timer"; 606 reg = <0xf8f00200 0x20>; 607 interrupts = <0x01 0x0b 0x301>; 608 interrupt-parent = <0x01>; 609 clocks = <0x02 0x04>; 610 phandle = <0x3d>; 611 }; 612 613 timer@f8001000 { 614 interrupt-parent = <0x01>; 615 interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; 616 compatible = "cdns,ttc"; 617 clocks = <0x02 0x06>; 618 reg = <0xf8001000 0x1000>; 619 phandle = <0x3e>; 620 }; 621 622 timer@f8002000 { 623 interrupt-parent = <0x01>; 624 interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; 625 compatible = "cdns,ttc"; 626 clocks = <0x02 0x06>; 627 reg = <0xf8002000 0x1000>; 628 phandle = <0x3f>; 629 }; 630 631 timer@f8f00600 { 632 interrupt-parent = <0x01>; 633 interrupts = <0x01 0x0d 0x301>; 634 compatible = "arm,cortex-a9-twd-timer"; 635 reg = <0xf8f00600 0x20>; 636 clocks = <0x02 0x04>; 637 phandle = <0x40>; 638 }; 639 640 usb@e0002000 { 641 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 642 status = "okay"; 643 clocks = <0x02 0x1c>; 644 interrupt-parent = <0x01>; 645 interrupts = <0x00 0x15 0x04>; 646 reg = <0xe0002000 0x1000>; 647 phy_type = "ulpi"; 648 dr_mode = "host"; 649 xlnx,phy-reset-gpio = <0x09 0x07 0x00>; 650 phandle = <0x41>; 651 }; 652 653 usb@e0003000 { 654 compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; 655 status = "disabled"; 656 clocks = <0x02 0x1d>; 657 interrupt-parent = <0x01>; 658 interrupts = <0x00 0x2c 0x04>; 659 reg = <0xe0003000 0x1000>; 660 phy_type = "ulpi"; 661 phandle = <0x42>; 662 }; 663 664 watchdog@f8005000 { 665 clocks = <0x02 0x2d>; 666 compatible = "cdns,wdt-r1p2"; 667 interrupt-parent = <0x01>; 668 interrupts = <0x00 0x09 0x01>; 669 reg = <0xf8005000 0x1000>; 670 timeout-sec = <0x0a>; 671 phandle = <0x43>; 672 }; 673 674 etb@f8801000 { 675 compatible = "arm,coresight-etb10\0arm,primecell"; 676 reg = <0xf8801000 0x1000>; 677 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 678 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 679 680 in-ports { 681 682 port { 683 684 endpoint { 685 remote-endpoint = <0x0d>; 686 phandle = <0x06>; 687 }; 688 }; 689 }; 690 }; 691 692 tpiu@f8803000 { 693 compatible = "arm,coresight-tpiu\0arm,primecell"; 694 reg = <0xf8803000 0x1000>; 695 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 696 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 697 698 in-ports { 699 700 port { 701 702 endpoint { 703 remote-endpoint = <0x0e>; 704 phandle = <0x05>; 705 }; 706 }; 707 }; 708 }; 709 710 funnel@f8804000 { 711 compatible = "arm,coresight-static-funnel\0arm,primecell"; 712 reg = <0xf8804000 0x1000>; 713 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 714 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 715 716 out-ports { 717 718 port { 719 720 endpoint { 721 remote-endpoint = <0x0f>; 722 phandle = <0x07>; 723 }; 724 }; 725 }; 726 727 in-ports { 728 #address-cells = <0x01>; 729 #size-cells = <0x00>; 730 731 port@0 { 732 reg = <0x00>; 733 734 endpoint { 735 remote-endpoint = <0x10>; 736 phandle = <0x13>; 737 }; 738 }; 739 740 port@1 { 741 reg = <0x01>; 742 743 endpoint { 744 remote-endpoint = <0x11>; 745 phandle = <0x15>; 746 }; 747 }; 748 749 port@2 { 750 reg = <0x02>; 751 752 endpoint { 753 phandle = <0x44>; 754 }; 755 }; 756 }; 757 }; 758 759 ptm@f889c000 { 760 compatible = "arm,coresight-etm3x\0arm,primecell"; 761 reg = <0xf889c000 0x1000>; 762 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 763 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 764 cpu = <0x12>; 765 766 out-ports { 767 768 port { 769 770 endpoint { 771 remote-endpoint = <0x13>; 772 phandle = <0x10>; 773 }; 774 }; 775 }; 776 }; 777 778 ptm@f889d000 { 779 compatible = "arm,coresight-etm3x\0arm,primecell"; 780 reg = <0xf889d000 0x1000>; 781 clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; 782 clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; 783 cpu = <0x14>; 784 785 out-ports { 786 787 port { 788 789 endpoint { 790 remote-endpoint = <0x15>; 791 phandle = <0x11>; 792 }; 793 }; 794 }; 795 }; 796 }; 797 798 aliases { 799 ethernet0 = "/axi/ethernet@e000b000"; 800 serial0 = "/axi/serial@e0001000"; 801 phandle = <0x45>; 802 }; 803 804 memory { 805 device_type = "memory"; 806 reg = <0x00 0x40000000>; 807 }; 808 809 chosen { 810 bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait"; 811 stdout-path = "/amba@0/uart@E0001000"; 812 }; 813 814 leds { 815 compatible = "gpio-leds"; 816 817 ds12 { 818 label = "ds12:green"; 819 gpios = <0x09 0x08 0x00>; 820 }; 821 822 ds15 { 823 label = "ds15:green"; 824 gpios = <0x09 0x3a 0x00>; 825 }; 826 827 ds16 { 828 label = "ds16:green"; 829 gpios = <0x09 0x3b 0x00>; 830 }; 831 832 ds17 { 833 label = "ds17:green"; 834 gpios = <0x09 0x3c 0x00>; 835 }; 836 837 ds18 { 838 label = "ds18:green"; 839 gpios = <0x09 0x3d 0x00>; 840 }; 841 842 ds19 { 843 label = "ds19:green"; 844 gpios = <0x09 0x3e 0x00>; 845 }; 846 847 ds20 { 848 label = "ds20:green"; 849 gpios = <0x09 0x3f 0x00>; 850 }; 851 852 ds21 { 853 label = "ds21:green"; 854 gpios = <0x09 0x40 0x00>; 855 }; 856 857 ds22 { 858 label = "ds22:green"; 859 gpios = <0x09 0x41 0x00>; 860 }; 861 862 ds23 { 863 label = "ds23:green"; 864 gpios = <0x09 0x0a 0x00>; 865 }; 866 }; 867 868 gpio_keys { 869 compatible = "gpio-keys"; 870 #address-cells = <0x01>; 871 #size-cells = <0x00>; 872 autorepeat; 873 874 sw5 { 875 label = "Left"; 876 linux,code = <0x69>; 877 gpios = <0x09 0x36 0x00>; 878 }; 879 880 sw7 { 881 label = "Right"; 882 linux,code = <0x6a>; 883 gpios = <0x09 0x37 0x00>; 884 }; 885 886 sw15_0 { 887 label = "SW15_0"; 888 linux,code = <0x0d>; 889 linux,input-type = <0x05>; 890 gpios = <0x09 0x38 0x00>; 891 }; 892 893 sw15_1 { 894 label = "SW15_1"; 895 linux,code = <0x01>; 896 linux,input-type = <0x05>; 897 gpios = <0x09 0x39 0x00>; 898 }; 899 900 sw13 { 901 label = "Select"; 902 linux,code = <0x1c>; 903 gpios = <0x09 0x0e 0x00>; 904 }; 905 906 sw14 { 907 label = "SW14"; 908 linux,code = <0x01>; 909 gpios = <0x09 0x0c 0x00>; 910 }; 911 }; 912 913 fpga-axi@0 { 914 compatible = "simple-bus"; 915 #address-cells = <0x01>; 916 #size-cells = <0x01>; 917 ranges; 918 phandle = <0x46>; 919 920 i2c@41600000 { 921 compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; 922 reg = <0x41600000 0x10000>; 923 interrupt-parent = <0x01>; 924 interrupts = <0x00 0x3a 0x04>; 925 clocks = <0x02 0x0f>; 926 clock-names = "pclk"; 927 #address-cells = <0x01>; 928 #size-cells = <0x00>; 929 930 mux@74 { 931 compatible = "pca9548"; 932 reg = <0x74>; 933 #address-cells = <0x01>; 934 #size-cells = <0x00>; 935 936 i2c@1 { 937 #size-cells = <0x00>; 938 #address-cells = <0x01>; 939 reg = <0x01>; 940 941 adv7511@39 { 942 compatible = "adi,adv7511"; 943 reg = <0x39 0x3f>; 944 reg-names = "primary\0edid"; 945 adi,input-depth = <0x08>; 946 adi,input-colorspace = "yuv422"; 947 adi,input-clock = "1x"; 948 adi,input-style = <0x01>; 949 adi,input-justification = "right"; 950 adi,clock-delay = <0x00>; 951 #sound-dai-cells = <0x01>; 952 phandle = <0x20>; 953 954 ports { 955 #address-cells = <0x01>; 956 #size-cells = <0x00>; 957 958 port@0 { 959 reg = <0x00>; 960 961 endpoint { 962 remote-endpoint = <0x16>; 963 phandle = <0x19>; 964 }; 965 }; 966 967 port@1 { 968 reg = <0x01>; 969 }; 970 }; 971 }; 972 }; 973 974 i2c@4 { 975 #size-cells = <0x00>; 976 #address-cells = <0x01>; 977 reg = <0x04>; 978 979 rtc@51 { 980 compatible = "rtc8564"; 981 reg = <0x51>; 982 }; 983 }; 984 985 i2c@5 { 986 #size-cells = <0x00>; 987 #address-cells = <0x01>; 988 reg = <0x05>; 989 phandle = <0x47>; 990 991 ad7291@2f { 992 compatible = "adi,ad7291"; 993 reg = <0x2f>; 994 }; 995 996 eeprom@50 { 997 compatible = "at24,24c02"; 998 reg = <0x50>; 999 }; 1000 }; 1001 }; 1002 }; 1003/* 1004 dma@43000000 { 1005 compatible = "adi,axi-dmac-1.00.a"; 1006 reg = <0x43000000 0x10000>; 1007 #dma-cells = <0x01>; 1008 interrupts = <0x00 0x3b 0x04>; 1009 clocks = <0x02 0x10>; 1010 phandle = <0x17>; 1011 1012 adi,channels { 1013 #size-cells = <0x00>; 1014 #address-cells = <0x01>; 1015 1016 dma-channel@0 { 1017 reg = <0x00>; 1018 adi,source-bus-width = <0x40>; 1019 adi,source-bus-type = <0x00>; 1020 adi,destination-bus-width = <0x40>; 1021 adi,destination-bus-type = <0x01>; 1022 }; 1023 }; 1024 }; 1025 1026 axi-clkgen@79000000 { 1027 compatible = "adi,axi-clkgen-2.00.a"; 1028 reg = <0x79000000 0x10000>; 1029 #clock-cells = <0x00>; 1030 clocks = <0x02 0x0f 0x02 0x10>; 1031 clock-names = "s_axi_aclk\0clkin1"; 1032 phandle = <0x18>; 1033 }; 1034 1035 axi_hdmi@70e00000 { 1036 compatible = "adi,axi-hdmi-tx-1.00.a"; 1037 reg = <0x70e00000 0x10000>; 1038 dmas = <0x17 0x00>; 1039 dma-names = "video"; 1040 clocks = <0x18>; 1041 1042 port { 1043 1044 endpoint { 1045 remote-endpoint = <0x19>; 1046 phandle = <0x16>; 1047 }; 1048 }; 1049 }; 1050 1051 axi-spdif-tx@75c00000 { 1052 compatible = "adi,axi-spdif-tx-1.00.a"; 1053 reg = <0x75c00000 0x1000>; 1054 dmas = <0x1a 0x00>; 1055 dma-names = "tx"; 1056 clocks = <0x02 0x0f 0x1b>; 1057 clock-names = "axi\0ref"; 1058 #sound-dai-cells = <0x00>; 1059 phandle = <0x1f>; 1060 }; 1061 1062 axi-sysid-0@45000000 { 1063 compatible = "adi,axi-sysid-1.00.a"; 1064 reg = <0x45000000 0x10000>; 1065 phandle = <0x48>; 1066 }; 1067 1068 dma@7c400000 { 1069 compatible = "adi,axi-dmac-1.00.a"; 1070 reg = <0x7c400000 0x10000>; 1071 #dma-cells = <0x01>; 1072 interrupts = <0x00 0x39 0x04>; 1073 clocks = <0x02 0x10>; 1074 phandle = <0x1c>; 1075 1076 adi,channels { 1077 #size-cells = <0x00>; 1078 #address-cells = <0x01>; 1079 1080 dma-channel@0 { 1081 reg = <0x00>; 1082 adi,source-bus-width = <0x40>; 1083 adi,source-bus-type = <0x02>; 1084 adi,destination-bus-width = <0x40>; 1085 adi,destination-bus-type = <0x00>; 1086 }; 1087 }; 1088 }; 1089 1090 dma@7c420000 { 1091 compatible = "adi,axi-dmac-1.00.a"; 1092 reg = <0x7c420000 0x10000>; 1093 #dma-cells = <0x01>; 1094 interrupts = <0x00 0x38 0x04>; 1095 clocks = <0x02 0x10>; 1096 phandle = <0x1e>; 1097 1098 adi,channels { 1099 #size-cells = <0x00>; 1100 #address-cells = <0x01>; 1101 1102 dma-channel@0 { 1103 reg = <0x00>; 1104 adi,source-bus-width = <0x40>; 1105 adi,source-bus-type = <0x00>; 1106 adi,destination-bus-width = <0x40>; 1107 adi,destination-bus-type = <0x02>; 1108 }; 1109 }; 1110 }; 1111*/ 1112 sdr: sdr { 1113 compatible ="sdr,sdr"; 1114 dmas = <&rx_dma 1 1115 &tx_dma 0>; 1116 dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; 1117 interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; 1118 interrupt-parent = <1>; 1119 interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; 1120 } ; 1121 1122 axidmatest_1: axidmatest@1 { 1123 compatible ="xlnx,axi-dma-test-1.00.a"; 1124 dmas = <&rx_dma 0 1125 &rx_dma 1>; 1126 dma-names = "axidma0", "axidma1"; 1127 } ; 1128 1129 tx_dma: dma@80400000 { 1130 #dma-cells = <1>; 1131 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 1132 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 1133 compatible = "xlnx,axi-dma-1.00.a"; 1134 interrupt-names = "mm2s_introut", "s2mm_introut"; 1135 interrupt-parent = <1>; 1136 interrupts = <0 35 4 0 36 4>; 1137 reg = <0x80400000 0x10000>; 1138 xlnx,addrwidth = <0x20>; 1139 xlnx,include-sg ; 1140 xlnx,sg-length-width = <0xe>; 1141 dma-channel@80400000 { 1142 compatible = "xlnx,axi-dma-mm2s-channel"; 1143 dma-channels = <0x1>; 1144 interrupts = <0 35 4>; 1145 xlnx,datawidth = <0x40>; 1146 xlnx,device-id = <0x0>; 1147 }; 1148 dma-channel@80400030 { 1149 compatible = "xlnx,axi-dma-s2mm-channel"; 1150 dma-channels = <0x1>; 1151 interrupts = <0 36 4>; 1152 xlnx,datawidth = <0x40>; 1153 xlnx,device-id = <0x0>; 1154 }; 1155 }; 1156 1157 rx_dma: dma@80410000 { 1158 #dma-cells = <1>; 1159 clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; 1160 clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; 1161 compatible = "xlnx,axi-dma-1.00.a"; 1162 //dma-coherent ; 1163 interrupt-names = "mm2s_introut", "s2mm_introut"; 1164 interrupt-parent = <1>; 1165 interrupts = <0 31 4 0 32 4>; 1166 reg = <0x80410000 0x10000>; 1167 xlnx,addrwidth = <0x20>; 1168 xlnx,include-sg ; 1169 xlnx,sg-length-width = <0xe>; 1170 dma-channel@80410000 { 1171 compatible = "xlnx,axi-dma-mm2s-channel"; 1172 dma-channels = <0x1>; 1173 interrupts = <0 31 4>; 1174 xlnx,datawidth = <0x40>; 1175 xlnx,device-id = <0x1>; 1176 }; 1177 dma-channel@80410030 { 1178 compatible = "xlnx,axi-dma-s2mm-channel"; 1179 dma-channels = <0x1>; 1180 interrupts = <0 32 4>; 1181 xlnx,datawidth = <0x40>; 1182 xlnx,device-id = <0x1>; 1183 }; 1184 }; 1185 1186 tx_intf_0: tx_intf@83c00000 { 1187 clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; 1188 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; 1189 compatible = "sdr,tx_intf"; 1190 interrupt-names = "tx_itrpt"; 1191 interrupt-parent = <1>; 1192 interrupts = <0 34 1>; 1193 reg = <0x83c00000 0x10000>; 1194 xlnx,s00-axi-addr-width = <0x7>; 1195 xlnx,s00-axi-data-width = <0x20>; 1196 }; 1197 1198 rx_intf_0: rx_intf@83c20000 { 1199 clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; 1200 clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; 1201 compatible = "sdr,rx_intf"; 1202 interrupt-names = "not_valid_anymore", "rx_pkt_intr"; 1203 interrupt-parent = <1>; 1204 interrupts = <0 29 1 0 30 1>; 1205 reg = <0x83c20000 0x10000>; 1206 xlnx,s00-axi-addr-width = <0x7>; 1207 xlnx,s00-axi-data-width = <0x20>; 1208 }; 1209 1210 openofdm_tx_0: openofdm_tx@83c10000 { 1211 clock-names = "clk"; 1212 clocks = <0x2 0x11>; 1213 compatible = "sdr,openofdm_tx"; 1214 reg = <0x83c10000 0x10000>; 1215 }; 1216 1217 openofdm_rx_0: openofdm_rx@83c30000 { 1218 clock-names = "clk"; 1219 clocks = <0x2 0x11>; 1220 compatible = "sdr,openofdm_rx"; 1221 reg = <0x83c30000 0x10000>; 1222 }; 1223 1224 xpu_0: xpu@83c40000 { 1225 clock-names = "s00_axi_aclk"; 1226 clocks = <0x2 0x11>; 1227 compatible = "sdr,xpu"; 1228 reg = <0x83c40000 0x10000>; 1229 }; 1230 1231 side_ch_0: side_ch@83c50000 { 1232 clock-names = "s00_axi_aclk"; 1233 clocks = <0x2 0x11>; 1234 compatible = "sdr,side_ch"; 1235 reg = <0x83c50000 0x10000>; 1236 dmas = <&rx_dma 0 1237 &tx_dma 1>; 1238 dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; 1239 }; 1240 1241 cf-ad9361-lpc@79020000 { 1242 compatible = "adi,axi-ad9361-6.00.a"; 1243 reg = <0x79020000 0x6000>; 1244 // dmas = <0x1c 0x00>; 1245 // dma-names = "rx"; 1246 spibus-connected = <0x1d>; 1247 phandle = <0x49>; 1248 }; 1249 1250 cf-ad9361-dds-core-lpc@79024000 { 1251 compatible = "adi,axi-ad9361-dds-6.00.a"; 1252 reg = <0x79024000 0x1000>; 1253 clocks = <0x1d 0x0d>; 1254 clock-names = "sampl_clk"; 1255 // dmas = <0x1e 0x00>; 1256 // dma-names = "tx"; 1257 phandle = <0x4a>; 1258 }; 1259 }; 1260/* 1261 audio_clock { 1262 compatible = "fixed-clock"; 1263 #clock-cells = <0x00>; 1264 clock-frequency = <0xbb8000>; 1265 phandle = <0x1b>; 1266 }; 1267 1268 adv7511_hdmi_snd { 1269 compatible = "simple-audio-card"; 1270 simple-audio-card,name = "HDMI monitor"; 1271 simple-audio-card,widgets = "Speaker\0Speaker"; 1272 simple-audio-card,routing = "Speaker\0TX"; 1273 1274 simple-audio-card,dai-link@0 { 1275 format = "spdif"; 1276 1277 cpu { 1278 sound-dai = <0x1f>; 1279 frame-master; 1280 bitclock-master; 1281 }; 1282 1283 codec { 1284 sound-dai = <0x20 0x01>; 1285 }; 1286 }; 1287 }; 1288*/ 1289 clocks { 1290 1291 clock@0 { 1292 compatible = "fixed-clock"; 1293 clock-frequency = <0x2625a00>; 1294 clock-output-names = "ad9361_ext_refclk"; 1295 #clock-cells = <0x00>; 1296 phandle = <0x08>; 1297 }; 1298 1299 clock@1 { 1300 compatible = "fixed-clock"; 1301 clock-frequency = <0x17d7840>; 1302 clock-output-names = "refclk"; 1303 #clock-cells = <0x00>; 1304 phandle = <0x0a>; 1305 }; 1306 }; 1307}; 1308