1 // Xianjun jiao. [email protected]; [email protected] 2 3 const char *sdr_compatible_str = "sdr,sdr"; 4 5 enum openwifi_band { 6 BAND_900M = 0, 7 BAND_2_4GHZ, 8 BAND_3_65GHZ, 9 BAND_5_0GHZ, 10 BAND_5_8GHZ, 11 BAND_5_9GHZ, 12 BAND_60GHZ, 13 }; 14 15 // ------------------------------------tx interface---------------------------------------- 16 const char *tx_intf_compatible_str = "sdr,tx_intf"; 17 18 #define TX_INTF_REG_MULTI_RST_ADDR (0*4) 19 #define TX_INTF_REG_MIXER_CFG_ADDR (1*4) 20 #define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 21 #define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 22 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) 23 #define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 24 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 25 #define TX_INTF_REG_MISC_SEL_ADDR (7*4) 26 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 27 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 28 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 29 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL1_ADDR (12*4) 30 #define TX_INTF_REG_BB_GAIN_ADDR (13*4) 31 #define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4) 32 #define TX_INTF_REG_ANT_SEL_ADDR (16*4) 33 #define TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR (21*4) 34 #define TX_INTF_REG_PKT_INFO_ADDR (22*4) 35 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (24*4) 36 37 #define TX_INTF_NUM_ANTENNA 2 38 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 39 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 40 41 enum tx_intf_mode { 42 TX_INTF_AXIS_LOOP_BACK = 0, 43 TX_INTF_BYPASS, 44 TX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 45 TX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 46 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 47 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 48 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 49 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 50 }; 51 52 const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10}; 53 54 struct tx_intf_driver_api { 55 u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); 56 57 u32 (*reg_read)(u32 reg); 58 void (*reg_write)(u32 reg, u32 value); 59 60 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 61 u32 (*TX_INTF_REG_MIXER_CFG_read)(void); 62 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 63 u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void); 64 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); 65 u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 66 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 67 u32 (*TX_INTF_REG_MISC_SEL_read)(void); 68 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 69 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 70 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 71 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 72 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 73 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 74 u32 (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read)(void); 75 u32 (*TX_INTF_REG_PKT_INFO_read)(void); 76 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 77 78 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 79 void (*TX_INTF_REG_MIXER_CFG_write)(u32 value); 80 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 81 void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 82 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); 83 void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 84 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 85 void (*TX_INTF_REG_MISC_SEL_write)(u32 value); 86 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 87 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 88 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 89 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); 90 void (*TX_INTF_REG_BB_GAIN_write)(u32 value); 91 void (*TX_INTF_REG_ANT_SEL_write)(u32 value); 92 void (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write)(u32 value); 93 void (*TX_INTF_REG_PKT_INFO_write)(u32 value); 94 }; 95 96 // ------------------------------------rx interface---------------------------------------- 97 const char *rx_intf_compatible_str = "sdr,rx_intf"; 98 99 #define RX_INTF_REG_MULTI_RST_ADDR (0*4) 100 #define RX_INTF_REG_MIXER_CFG_ADDR (1*4) 101 #define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4) 102 #define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 103 #define RX_INTF_REG_IQ_CTRL_ADDR (4*4) 104 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 105 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4) 106 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4) 107 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 108 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 109 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 110 #define RX_INTF_REG_BB_GAIN_ADDR (11*4) 111 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4) 112 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4) 113 #define RX_INTF_REG_ANT_SEL_ADDR (16*4) 114 115 #define RX_INTF_NUM_ANTENNA 2 116 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 117 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 118 119 enum rx_intf_mode { 120 RX_INTF_AXIS_LOOP_BACK = 0, 121 RX_INTF_BYPASS, 122 RX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 123 RX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 124 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 125 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 126 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 127 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 128 }; 129 130 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10}; 131 132 struct rx_intf_driver_api { 133 u32 io_start; 134 u32 base_addr; 135 136 u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); 137 138 u32 (*reg_read)(u32 reg); 139 void (*reg_write)(u32 reg, u32 value); 140 141 u32 (*RX_INTF_REG_MULTI_RST_read)(void); 142 u32 (*RX_INTF_REG_MIXER_CFG_read)(void); 143 u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void); 144 u32 (*RX_INTF_REG_IQ_CTRL_read)(void); 145 u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 146 u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void); 147 u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void); 148 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 149 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 150 u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 151 u32 (*RX_INTF_REG_ANT_SEL_read)(void); 152 u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void); 153 void (*RX_INTF_REG_MULTI_RST_write)(u32 value); 154 void (*RX_INTF_REG_MIXER_CFG_write)(u32 value); 155 void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 156 void (*RX_INTF_REG_IQ_CTRL_write)(u32 value); 157 void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 158 void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value); 159 void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value); 160 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 161 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 162 void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 163 void (*RX_INTF_REG_BB_GAIN_write)(u32 value); 164 void (*RX_INTF_REG_ANT_SEL_write)(u32 value); 165 void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value); 166 167 void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value); 168 void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value); 169 void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value); 170 }; 171 172 // ----------------------------------openofdm rx------------------------------- 173 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; 174 175 #define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4) 176 #define OPENOFDM_RX_REG_ENABLE_ADDR (1*4) 177 #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) 178 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) 179 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) 180 181 enum openofdm_rx_mode { 182 OPENOFDM_RX_TEST = 0, 183 OPENOFDM_RX_NORMAL, 184 }; 185 186 struct openofdm_rx_driver_api { 187 u32 power_thres; 188 u32 min_plateau; 189 190 u32 (*hw_init)(enum openofdm_rx_mode mode); 191 192 u32 (*reg_read)(u32 reg); 193 void (*reg_write)(u32 reg, u32 value); 194 195 u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void); 196 197 void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value); 198 void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value); 199 void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); 200 void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); 201 }; 202 203 // ---------------------------------------openofdm tx------------------------------- 204 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx"; 205 206 #define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4) 207 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4) 208 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4) 209 210 enum openofdm_tx_mode { 211 OPENOFDM_TX_TEST = 0, 212 OPENOFDM_TX_NORMAL, 213 }; 214 215 struct openofdm_tx_driver_api { 216 u32 (*hw_init)(enum openofdm_tx_mode mode); 217 218 u32 (*reg_read)(u32 reg); 219 void (*reg_write)(u32 reg, u32 value); 220 221 void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value); 222 void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value); 223 void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value); 224 }; 225 226 // ---------------------------------------xpu low MAC controller------------------------------- 227 228 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h 229 #define UNICAST_FOR_US (1<<9) 230 #define BROADCAST_ALL_ONE (1<<10) 231 #define BROADCAST_ALL_ZERO (1<<11) 232 #define MY_BEACON (1<<12) 233 #define MONITOR_ALL (1<<13) 234 235 const char *xpu_compatible_str = "sdr,xpu"; 236 237 #define XPU_REG_MULTI_RST_ADDR (0*4) 238 #define XPU_REG_SRC_SEL_ADDR (1*4) 239 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) 240 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) 241 #define XPU_REG_BAND_CHANNEL_ADDR (4*4) 242 #define XPU_REG_RSSI_DB_CFG_ADDR (7*4) 243 #define XPU_REG_LBT_TH_ADDR (8*4) 244 #define XPU_REG_CSMA_DEBUG_ADDR (9*4) 245 #define XPU_REG_BB_RF_DELAY_ADDR (10*4) 246 #define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4) 247 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) 248 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) 249 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) 250 #define XPU_REG_CSMA_CFG_ADDR (19*4) 251 252 #define XPU_REG_SLICE_COUNT_TOTAL0_ADDR (20*4) 253 #define XPU_REG_SLICE_COUNT_START0_ADDR (21*4) 254 #define XPU_REG_SLICE_COUNT_END0_ADDR (22*4) 255 #define XPU_REG_SLICE_COUNT_TOTAL1_ADDR (23*4) 256 #define XPU_REG_SLICE_COUNT_START1_ADDR (24*4) 257 #define XPU_REG_SLICE_COUNT_END1_ADDR (25*4) 258 259 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4) 260 #define XPU_REG_FILTER_FLAG_ADDR (27*4) 261 #define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4) 262 #define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4) 263 #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) 264 #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) 265 266 #define XPU_REG_FC_DI_ADDR (34*4) 267 #define XPU_REG_ADDR1_LOW_ADDR (35*4) 268 #define XPU_REG_ADDR1_HIGH_ADDR (36*4) 269 #define XPU_REG_ADDR2_LOW_ADDR (37*4) 270 #define XPU_REG_ADDR2_HIGH_ADDR (38*4) 271 #define XPU_REG_ADDR3_LOW_ADDR (39*4) 272 #define XPU_REG_ADDR3_HIGH_ADDR (40*4) 273 274 #define XPU_REG_SC_LOW_ADDR (41*4) 275 #define XPU_REG_ADDR4_HIGH_ADDR (42*4) 276 #define XPU_REG_ADDR4_LOW_ADDR (43*4) 277 278 #define XPU_REG_TRX_STATUS_ADDR (50*4) 279 #define XPU_REG_TX_RESULT_ADDR (51*4) 280 281 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) 282 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) 283 284 #define XPU_REG_RSSI_HALF_DB_ADDR (60*4) 285 #define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4) 286 287 enum xpu_mode { 288 XPU_TEST = 0, 289 XPU_NORMAL, 290 }; 291 292 struct xpu_driver_api { 293 u32 (*hw_init)(enum xpu_mode mode); 294 295 u32 (*reg_read)(u32 reg); 296 void (*reg_write)(u32 reg, u32 value); 297 298 void (*XPU_REG_MULTI_RST_write)(u32 value); 299 u32 (*XPU_REG_MULTI_RST_read)(void); 300 301 void (*XPU_REG_SRC_SEL_write)(u32 value); 302 u32 (*XPU_REG_SRC_SEL_read)(void); 303 304 void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value); 305 u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void); 306 307 void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value); 308 u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void); 309 310 void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value); 311 u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void); 312 313 void (*XPU_REG_ACK_FC_FILTER_write)(u32 value); 314 u32 (*XPU_REG_ACK_FC_FILTER_read)(void); 315 316 void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value); 317 u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void); 318 319 void (*XPU_REG_FILTER_FLAG_write)(u32 value); 320 u32 (*XPU_REG_FILTER_FLAG_read)(void); 321 322 void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value); 323 u32 (*XPU_REG_MAC_ADDR_LOW_read)(void); 324 325 void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value); 326 u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void); 327 328 void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value); 329 u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void); 330 331 void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value); 332 u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void); 333 334 void (*XPU_REG_BAND_CHANNEL_write)(u32 value); 335 u32 (*XPU_REG_BAND_CHANNEL_read)(void); 336 337 u32 (*XPU_REG_TRX_STATUS_read)(void); 338 u32 (*XPU_REG_TX_RESULT_read)(void); 339 340 u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void); 341 u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void); 342 343 void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value); 344 void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value); 345 void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value); 346 347 u32 (*XPU_REG_FC_DI_read)(void); 348 u32 (*XPU_REG_ADDR1_LOW_read)(void); 349 u32 (*XPU_REG_ADDR1_HIGH_read)(void); 350 u32 (*XPU_REG_ADDR2_LOW_read)(void); 351 u32 (*XPU_REG_ADDR2_HIGH_read)(void); 352 353 void (*XPU_REG_LBT_TH_write)(u32 value); 354 u32 (*XPU_REG_LBT_TH_read)(void); 355 356 void (*XPU_REG_RSSI_DB_CFG_write)(u32 value); 357 u32 (*XPU_REG_RSSI_DB_CFG_read)(void); 358 359 void (*XPU_REG_CSMA_DEBUG_write)(u32 value); 360 u32 (*XPU_REG_CSMA_DEBUG_read)(void); 361 362 void (*XPU_REG_CSMA_CFG_write)(u32 value); 363 u32 (*XPU_REG_CSMA_CFG_read)(void); 364 365 void (*XPU_REG_SLICE_COUNT_TOTAL0_write)(u32 value); 366 void (*XPU_REG_SLICE_COUNT_START0_write)(u32 value); 367 void (*XPU_REG_SLICE_COUNT_END0_write)(u32 value); 368 void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value); 369 void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value); 370 void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value); 371 372 u32 (*XPU_REG_SLICE_COUNT_TOTAL0_read)(void); 373 u32 (*XPU_REG_SLICE_COUNT_START0_read)(void); 374 u32 (*XPU_REG_SLICE_COUNT_END0_read)(void); 375 u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void); 376 u32 (*XPU_REG_SLICE_COUNT_START1_read)(void); 377 u32 (*XPU_REG_SLICE_COUNT_END1_read)(void); 378 379 void (*XPU_REG_BB_RF_DELAY_write)(u32 value); 380 void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value); 381 382 void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr); 383 }; 384