1 // Author: Xianjun jiao, Michael Mehari, Wei Liu 2 // SPDX-FileCopyrightText: 2019 UGent 3 // SPDX-License-Identifier: AGPL-3.0-or-later 4 5 // #ifndef __HW_DEF_H_FILE__ 6 // #define __HW_DEF_H_FILE__ 7 const char *sdr_compatible_str = "sdr,sdr"; 8 9 enum openwifi_fpga_type { 10 SMALL_FPGA = 0, 11 LARGE_FPGA = 1, 12 }; 13 14 enum openwifi_band { 15 BAND_900M = 0, 16 BAND_2_4GHZ, 17 BAND_3_65GHZ, 18 BAND_5_0GHZ, 19 BAND_5_8GHZ, 20 BAND_5_9GHZ, 21 BAND_60GHZ, 22 }; 23 24 // ------------------------------------tx interface---------------------------------------- 25 const char *tx_intf_compatible_str = "sdr,tx_intf"; 26 27 #define TX_INTF_REG_MULTI_RST_ADDR (0*4) 28 #define TX_INTF_REG_ARBITRARY_IQ_ADDR (1*4) 29 #define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 30 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) 31 #define TX_INTF_REG_CSI_FUZZER_ADDR (5*4) 32 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 33 #define TX_INTF_REG_ARBITRARY_IQ_CTL_ADDR (7*4) 34 #define TX_INTF_REG_TX_CONFIG_ADDR (8*4) 35 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 36 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 37 #define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4) 38 #define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4) 39 #define TX_INTF_REG_BB_GAIN_ADDR (13*4) 40 #define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4) 41 #define TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR (15*4) 42 #define TX_INTF_REG_ANT_SEL_ADDR (16*4) 43 #define TX_INTF_REG_PHY_HDR_CONFIG_ADDR (17*4) 44 #define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4) 45 #define TX_INTF_REG_PKT_INFO1_ADDR (22*4) 46 #define TX_INTF_REG_PKT_INFO2_ADDR (23*4) 47 #define TX_INTF_REG_PKT_INFO3_ADDR (24*4) 48 #define TX_INTF_REG_PKT_INFO4_ADDR (25*4) 49 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (26*4) 50 51 #define TX_INTF_NUM_ANTENNA 2 52 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 53 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 54 55 enum tx_intf_mode { 56 TX_INTF_AXIS_LOOP_BACK = 0, 57 TX_INTF_BYPASS, 58 TX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 59 TX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 60 TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH, 61 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 62 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 63 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 64 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 65 }; 66 67 const int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10}; 68 const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v 69 70 struct tx_intf_driver_api { 71 u32 (*hw_init)(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type); 72 73 u32 (*reg_read)(u32 reg); 74 void (*reg_write)(u32 reg, u32 value); 75 76 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 77 u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void); 78 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 79 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); 80 u32 (*TX_INTF_REG_CSI_FUZZER_read)(void); 81 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 82 u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void); 83 u32 (*TX_INTF_REG_TX_CONFIG_read)(void); 84 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 85 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 86 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void); 87 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void); 88 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 89 u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void); 90 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 91 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 92 u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void); 93 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void); 94 u32 (*TX_INTF_REG_PKT_INFO1_read)(void); 95 u32 (*TX_INTF_REG_PKT_INFO2_read)(void); 96 u32 (*TX_INTF_REG_PKT_INFO3_read)(void); 97 u32 (*TX_INTF_REG_PKT_INFO4_read)(void); 98 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 99 100 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 101 void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value); 102 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 103 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); 104 void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value); 105 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 106 void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value); 107 void (*TX_INTF_REG_TX_CONFIG_write)(u32 value); 108 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 109 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 110 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value); 111 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value); 112 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); 113 void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value); 114 void (*TX_INTF_REG_BB_GAIN_write)(u32 value); 115 void (*TX_INTF_REG_ANT_SEL_write)(u32 value); 116 void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value); 117 void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value); 118 void (*TX_INTF_REG_PKT_INFO1_write)(u32 value); 119 void (*TX_INTF_REG_PKT_INFO2_write)(u32 value); 120 void (*TX_INTF_REG_PKT_INFO3_write)(u32 value); 121 void (*TX_INTF_REG_PKT_INFO4_write)(u32 value); 122 }; 123 124 // ------------------------------------rx interface---------------------------------------- 125 const char *rx_intf_compatible_str = "sdr,rx_intf"; 126 127 #define RX_INTF_REG_MULTI_RST_ADDR (0*4) 128 #define RX_INTF_REG_MIXER_CFG_ADDR (1*4) 129 #define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4) 130 #define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 131 #define RX_INTF_REG_IQ_CTRL_ADDR (4*4) 132 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 133 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4) 134 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4) 135 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 136 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 137 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 138 #define RX_INTF_REG_BB_GAIN_ADDR (11*4) 139 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4) 140 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4) 141 #define RX_INTF_REG_ANT_SEL_ADDR (16*4) 142 143 #define RX_INTF_NUM_ANTENNA 2 144 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 145 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 146 147 enum rx_intf_mode { 148 RX_INTF_AXIS_LOOP_BACK = 0, 149 RX_INTF_BYPASS, 150 RX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 151 RX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 152 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 153 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 154 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 155 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 156 }; 157 158 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10}; 159 160 struct rx_intf_driver_api { 161 u32 io_start; 162 u32 base_addr; 163 164 u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); 165 166 u32 (*reg_read)(u32 reg); 167 void (*reg_write)(u32 reg, u32 value); 168 169 u32 (*RX_INTF_REG_MULTI_RST_read)(void); 170 u32 (*RX_INTF_REG_MIXER_CFG_read)(void); 171 u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void); 172 u32 (*RX_INTF_REG_IQ_CTRL_read)(void); 173 u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 174 u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void); 175 u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void); 176 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 177 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 178 u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 179 u32 (*RX_INTF_REG_ANT_SEL_read)(void); 180 u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void); 181 void (*RX_INTF_REG_MULTI_RST_write)(u32 value); 182 void (*RX_INTF_REG_MIXER_CFG_write)(u32 value); 183 void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 184 void (*RX_INTF_REG_IQ_CTRL_write)(u32 value); 185 void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 186 void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value); 187 void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value); 188 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 189 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 190 void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 191 void (*RX_INTF_REG_BB_GAIN_write)(u32 value); 192 void (*RX_INTF_REG_ANT_SEL_write)(u32 value); 193 void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value); 194 195 void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value); 196 void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value); 197 void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value); 198 }; 199 200 // ----------------------------------openofdm rx------------------------------- 201 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; 202 203 #define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4) 204 #define OPENOFDM_RX_REG_ENABLE_ADDR (1*4) 205 #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) 206 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) 207 #define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4) 208 #define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4) 209 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) 210 211 enum openofdm_rx_mode { 212 OPENOFDM_RX_TEST = 0, 213 OPENOFDM_RX_NORMAL, 214 }; 215 216 #define OPENOFDM_RX_POWER_THRES_INIT 124 217 // Above 118 is based on these test result (2022-03-09) 218 // FMCOMMS3 219 // 2437M 220 // 11a/g BPSK 6M, Rx sensitivity level dmesg report -85dBm 221 // priv->rssi_correction = 153; rssi_half_db/2 = 153-85=68; rssi_half_db = 136 222 // 5180M 223 // 11a/g BPSK 6m, Rx sensitivity level dmesg report -84dBm 224 // priv->rssi_correction = 145; rssi_half_db/2 = 145-84=61; rssi_half_db = 122 225 // 5320M 226 // 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm 227 // priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124 228 229 // FMCOMMS2 230 // 2437M 231 // 11a/g BPSK 6M, Rx sensitivity level dmesg report -80dBm 232 // priv->rssi_correction = 153; rssi_half_db/2 = 153-80=73; rssi_half_db = 146 233 // 5180M 234 // 11a/g BPSK 6m, Rx sensitivity level dmesg report -83dBm 235 // priv->rssi_correction = 145; rssi_half_db/2 = 145-83=62; rssi_half_db = 124 236 // 5320M 237 // 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm 238 // priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124 239 240 #define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-85) //-85 will remove lots of false alarm. the best openwifi reported sensitivity is like -90/-92 (set it manually if conductive test with wifi tester) 241 #define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64 242 #define OPENOFDM_RX_MIN_PLATEAU_INIT 100 243 #define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 1 244 #define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48 245 246 #define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf 247 248 #define OPENWIFI_MIN_SIGNAL_LEN_TH 14 //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf 249 //due to CRC32, at least 4 bytes needed to push out expected CRC result 250 251 struct openofdm_rx_driver_api { 252 u32 (*hw_init)(enum openofdm_rx_mode mode); 253 254 u32 (*reg_read)(u32 reg); 255 void (*reg_write)(u32 reg, u32 value); 256 257 u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void); 258 259 void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value); 260 void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value); 261 void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); 262 void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); 263 void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value); 264 void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value); 265 }; 266 267 // ---------------------------------------openofdm tx------------------------------- 268 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx"; 269 270 #define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4) 271 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4) 272 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4) 273 274 enum openofdm_tx_mode { 275 OPENOFDM_TX_TEST = 0, 276 OPENOFDM_TX_NORMAL, 277 }; 278 279 struct openofdm_tx_driver_api { 280 u32 (*hw_init)(enum openofdm_tx_mode mode); 281 282 u32 (*reg_read)(u32 reg); 283 void (*reg_write)(u32 reg, u32 value); 284 285 void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value); 286 void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value); 287 void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value); 288 }; 289 290 // ---------------------------------------xpu low MAC controller------------------------------- 291 292 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h 293 #define UNICAST_FOR_US (1<<9) 294 #define BROADCAST_ALL_ONE (1<<10) 295 #define BROADCAST_ALL_ZERO (1<<11) 296 #define MY_BEACON (1<<12) 297 #define MONITOR_ALL (1<<13) 298 299 const char *xpu_compatible_str = "sdr,xpu"; 300 301 #define XPU_REG_MULTI_RST_ADDR (0*4) 302 #define XPU_REG_SRC_SEL_ADDR (1*4) 303 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) 304 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) 305 #define XPU_REG_BAND_CHANNEL_ADDR (4*4) 306 #define XPU_REG_DIFS_ADVANCE_ADDR (5*4) 307 #define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4) 308 #define XPU_REG_RSSI_DB_CFG_ADDR (7*4) 309 #define XPU_REG_LBT_TH_ADDR (8*4) 310 #define XPU_REG_CSMA_DEBUG_ADDR (9*4) 311 #define XPU_REG_BB_RF_DELAY_ADDR (10*4) 312 #define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4) 313 #define XPU_REG_AMPDU_ACTION_ADDR (12*4) 314 #define XPU_REG_SPI_DISABLE_ADDR (13*4) 315 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) 316 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) 317 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) 318 #define XPU_REG_CSMA_CFG_ADDR (19*4) 319 320 #define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) 321 #define XPU_REG_SLICE_COUNT_START_ADDR (21*4) 322 #define XPU_REG_SLICE_COUNT_END_ADDR (22*4) 323 324 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4) 325 #define XPU_REG_FILTER_FLAG_ADDR (27*4) 326 #define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4) 327 #define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4) 328 #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) 329 #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) 330 331 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) 332 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) 333 334 #define XPU_REG_MAC_ADDR_READ_BACK_ADDR (62*4) 335 #define XPU_REG_FPGA_GIT_REV_ADDR (63*4) 336 337 enum xpu_mode { 338 XPU_TEST = 0, 339 XPU_NORMAL, 340 }; 341 342 struct xpu_driver_api { 343 u32 (*hw_init)(enum xpu_mode mode); 344 345 u32 (*reg_read)(u32 reg); 346 void (*reg_write)(u32 reg, u32 value); 347 348 void (*XPU_REG_MULTI_RST_write)(u32 value); 349 u32 (*XPU_REG_MULTI_RST_read)(void); 350 351 void (*XPU_REG_SRC_SEL_write)(u32 value); 352 u32 (*XPU_REG_SRC_SEL_read)(void); 353 354 void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value); 355 u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void); 356 357 void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value); 358 u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void); 359 360 void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value); 361 u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void); 362 363 void (*XPU_REG_ACK_FC_FILTER_write)(u32 value); 364 u32 (*XPU_REG_ACK_FC_FILTER_read)(void); 365 366 void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value); 367 u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void); 368 369 void (*XPU_REG_FILTER_FLAG_write)(u32 value); 370 u32 (*XPU_REG_FILTER_FLAG_read)(void); 371 372 void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value); 373 u32 (*XPU_REG_MAC_ADDR_LOW_read)(void); 374 375 void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value); 376 u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void); 377 378 void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value); 379 u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void); 380 381 void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value); 382 u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void); 383 384 void (*XPU_REG_BAND_CHANNEL_write)(u32 value); 385 u32 (*XPU_REG_BAND_CHANNEL_read)(void); 386 387 void (*XPU_REG_DIFS_ADVANCE_write)(u32 value); 388 u32 (*XPU_REG_DIFS_ADVANCE_read)(void); 389 390 void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value); 391 u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void); 392 393 u32 (*XPU_REG_TRX_STATUS_read)(void); 394 u32 (*XPU_REG_TX_RESULT_read)(void); 395 396 u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void); 397 u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void); 398 399 void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value); 400 void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value); 401 void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value); 402 403 u32 (*XPU_REG_FC_DI_read)(void); 404 u32 (*XPU_REG_ADDR1_LOW_read)(void); 405 u32 (*XPU_REG_ADDR1_HIGH_read)(void); 406 u32 (*XPU_REG_ADDR2_LOW_read)(void); 407 u32 (*XPU_REG_ADDR2_HIGH_read)(void); 408 409 void (*XPU_REG_LBT_TH_write)(u32 value); 410 u32 (*XPU_REG_LBT_TH_read)(void); 411 412 void (*XPU_REG_RSSI_DB_CFG_write)(u32 value); 413 u32 (*XPU_REG_RSSI_DB_CFG_read)(void); 414 415 void (*XPU_REG_CSMA_DEBUG_write)(u32 value); 416 u32 (*XPU_REG_CSMA_DEBUG_read)(void); 417 418 void (*XPU_REG_CSMA_CFG_write)(u32 value); 419 u32 (*XPU_REG_CSMA_CFG_read)(void); 420 421 void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value); 422 void (*XPU_REG_SLICE_COUNT_START_write)(u32 value); 423 void (*XPU_REG_SLICE_COUNT_END_write)(u32 value); 424 void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value); 425 void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value); 426 void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value); 427 428 u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void); 429 u32 (*XPU_REG_SLICE_COUNT_START_read)(void); 430 u32 (*XPU_REG_SLICE_COUNT_END_read)(void); 431 u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void); 432 u32 (*XPU_REG_SLICE_COUNT_START1_read)(void); 433 u32 (*XPU_REG_SLICE_COUNT_END1_read)(void); 434 435 void (*XPU_REG_BB_RF_DELAY_write)(u32 value); 436 437 void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value); 438 u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void); 439 440 void (*XPU_REG_SPI_DISABLE_write)(u32 value); 441 u32 (*XPU_REG_SPI_DISABLE_read)(void); 442 443 void (*XPU_REG_AMPDU_ACTION_write)(u32 value); 444 u32 (*XPU_REG_AMPDU_ACTION_read)(void); 445 446 void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr); 447 }; 448 449 // #endif 450