1 // Author: Xianjun jiao, Michael Mehari, Wei Liu 2 // SPDX-FileCopyrightText: 2019 UGent 3 // SPDX-License-Identifier: AGPL-3.0-or-later 4 5 // #ifndef __HW_DEF_H_FILE__ 6 // #define __HW_DEF_H_FILE__ 7 const char *sdr_compatible_str = "sdr,sdr"; 8 9 enum openwifi_fpga_type { 10 SMALL_FPGA = 0, 11 LARGE_FPGA = 1, 12 }; 13 14 enum openwifi_band { 15 BAND_900M = 0, 16 BAND_2_4GHZ, 17 BAND_3_65GHZ, 18 BAND_5_0GHZ, 19 BAND_5_8GHZ, 20 BAND_5_9GHZ, 21 BAND_60GHZ, 22 }; 23 24 // ------------------------------------tx interface---------------------------------------- 25 const char *tx_intf_compatible_str = "sdr,tx_intf"; 26 27 #define TX_INTF_REG_MULTI_RST_ADDR (0*4) 28 #define TX_INTF_REG_MIXER_CFG_ADDR (1*4) 29 #define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4) 30 #define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 31 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4) 32 #define TX_INTF_REG_CSI_FUZZER_ADDR (5*4) 33 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4) 34 #define TX_INTF_REG_MISC_SEL_ADDR (7*4) 35 #define TX_INTF_REG_TX_CONFIG_ADDR (8*4) 36 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 37 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 38 #define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4) 39 #define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4) 40 #define TX_INTF_REG_BB_GAIN_ADDR (13*4) 41 #define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4) 42 #define TX_INTF_REG_AMPDU_ACTION_CONFIG_ADDR (15*4) 43 #define TX_INTF_REG_ANT_SEL_ADDR (16*4) 44 #define TX_INTF_REG_PHY_HDR_CONFIG_ADDR (17*4) 45 #define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4) 46 #define TX_INTF_REG_PKT_INFO1_ADDR (22*4) 47 #define TX_INTF_REG_PKT_INFO2_ADDR (23*4) 48 #define TX_INTF_REG_PKT_INFO3_ADDR (24*4) 49 #define TX_INTF_REG_PKT_INFO4_ADDR (25*4) 50 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (26*4) 51 52 #define TX_INTF_NUM_ANTENNA 2 53 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 54 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 55 56 enum tx_intf_mode { 57 TX_INTF_AXIS_LOOP_BACK = 0, 58 TX_INTF_BYPASS, 59 TX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 60 TX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 61 TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH, 62 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 63 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 64 TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 65 TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 66 }; 67 68 const int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10}; 69 const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v 70 71 struct tx_intf_driver_api { 72 u32 (*hw_init)(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type); 73 74 u32 (*reg_read)(u32 reg); 75 void (*reg_write)(u32 reg, u32 value); 76 77 u32 (*TX_INTF_REG_MULTI_RST_read)(void); 78 u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void); 79 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void); 80 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void); 81 u32 (*TX_INTF_REG_CSI_FUZZER_read)(void); 82 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void); 83 u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void); 84 u32 (*TX_INTF_REG_TX_CONFIG_read)(void); 85 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 86 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 87 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void); 88 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void); 89 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void); 90 u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void); 91 u32 (*TX_INTF_REG_BB_GAIN_read)(void); 92 u32 (*TX_INTF_REG_ANT_SEL_read)(void); 93 u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void); 94 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void); 95 u32 (*TX_INTF_REG_PKT_INFO1_read)(void); 96 u32 (*TX_INTF_REG_PKT_INFO2_read)(void); 97 u32 (*TX_INTF_REG_PKT_INFO3_read)(void); 98 u32 (*TX_INTF_REG_PKT_INFO4_read)(void); 99 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void); 100 101 void (*TX_INTF_REG_MULTI_RST_write)(u32 value); 102 void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value); 103 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value); 104 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value); 105 void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value); 106 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value); 107 void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value); 108 void (*TX_INTF_REG_TX_CONFIG_write)(u32 value); 109 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 110 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 111 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value); 112 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value); 113 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value); 114 void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value); 115 void (*TX_INTF_REG_BB_GAIN_write)(u32 value); 116 void (*TX_INTF_REG_ANT_SEL_write)(u32 value); 117 void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value); 118 void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value); 119 void (*TX_INTF_REG_PKT_INFO1_write)(u32 value); 120 void (*TX_INTF_REG_PKT_INFO2_write)(u32 value); 121 void (*TX_INTF_REG_PKT_INFO3_write)(u32 value); 122 void (*TX_INTF_REG_PKT_INFO4_write)(u32 value); 123 }; 124 125 // ------------------------------------rx interface---------------------------------------- 126 const char *rx_intf_compatible_str = "sdr,rx_intf"; 127 128 #define RX_INTF_REG_MULTI_RST_ADDR (0*4) 129 #define RX_INTF_REG_MIXER_CFG_ADDR (1*4) 130 #define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4) 131 #define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4) 132 #define RX_INTF_REG_IQ_CTRL_ADDR (4*4) 133 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4) 134 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4) 135 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4) 136 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4) 137 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4) 138 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4) 139 #define RX_INTF_REG_BB_GAIN_ADDR (11*4) 140 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4) 141 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4) 142 #define RX_INTF_REG_ANT_SEL_ADDR (16*4) 143 144 #define RX_INTF_NUM_ANTENNA 2 145 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8) 146 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3 147 148 enum rx_intf_mode { 149 RX_INTF_AXIS_LOOP_BACK = 0, 150 RX_INTF_BYPASS, 151 RX_INTF_BW_20MHZ_AT_0MHZ_ANT0, 152 RX_INTF_BW_20MHZ_AT_0MHZ_ANT1, 153 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0, 154 RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 155 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0, 156 RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 157 }; 158 159 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10}; 160 161 struct rx_intf_driver_api { 162 u32 io_start; 163 u32 base_addr; 164 165 u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps); 166 167 u32 (*reg_read)(u32 reg); 168 void (*reg_write)(u32 reg, u32 value); 169 170 u32 (*RX_INTF_REG_MULTI_RST_read)(void); 171 u32 (*RX_INTF_REG_MIXER_CFG_read)(void); 172 u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void); 173 u32 (*RX_INTF_REG_IQ_CTRL_read)(void); 174 u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void); 175 u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void); 176 u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void); 177 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void); 178 u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void); 179 u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void); 180 u32 (*RX_INTF_REG_ANT_SEL_read)(void); 181 u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void); 182 void (*RX_INTF_REG_MULTI_RST_write)(u32 value); 183 void (*RX_INTF_REG_MIXER_CFG_write)(u32 value); 184 void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value); 185 void (*RX_INTF_REG_IQ_CTRL_write)(u32 value); 186 void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value); 187 void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value); 188 void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value); 189 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value); 190 void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value); 191 void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value); 192 void (*RX_INTF_REG_BB_GAIN_write)(u32 value); 193 void (*RX_INTF_REG_ANT_SEL_write)(u32 value); 194 void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value); 195 196 void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value); 197 void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value); 198 void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value); 199 }; 200 201 // ----------------------------------openofdm rx------------------------------- 202 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; 203 204 #define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4) 205 #define OPENOFDM_RX_REG_ENABLE_ADDR (1*4) 206 #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) 207 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) 208 #define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4) 209 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) 210 211 enum openofdm_rx_mode { 212 OPENOFDM_RX_TEST = 0, 213 OPENOFDM_RX_NORMAL, 214 }; 215 216 struct openofdm_rx_driver_api { 217 u32 (*hw_init)(enum openofdm_rx_mode mode); 218 219 u32 (*reg_read)(u32 reg); 220 void (*reg_write)(u32 reg, u32 value); 221 222 u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void); 223 224 void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value); 225 void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value); 226 void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); 227 void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); 228 void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value); 229 }; 230 231 // ---------------------------------------openofdm tx------------------------------- 232 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx"; 233 234 #define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4) 235 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4) 236 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4) 237 238 enum openofdm_tx_mode { 239 OPENOFDM_TX_TEST = 0, 240 OPENOFDM_TX_NORMAL, 241 }; 242 243 struct openofdm_tx_driver_api { 244 u32 (*hw_init)(enum openofdm_tx_mode mode); 245 246 u32 (*reg_read)(u32 reg); 247 void (*reg_write)(u32 reg, u32 value); 248 249 void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value); 250 void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value); 251 void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value); 252 }; 253 254 // ---------------------------------------xpu low MAC controller------------------------------- 255 256 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h 257 #define UNICAST_FOR_US (1<<9) 258 #define BROADCAST_ALL_ONE (1<<10) 259 #define BROADCAST_ALL_ZERO (1<<11) 260 #define MY_BEACON (1<<12) 261 #define MONITOR_ALL (1<<13) 262 263 const char *xpu_compatible_str = "sdr,xpu"; 264 265 #define XPU_REG_MULTI_RST_ADDR (0*4) 266 #define XPU_REG_SRC_SEL_ADDR (1*4) 267 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4) 268 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4) 269 #define XPU_REG_BAND_CHANNEL_ADDR (4*4) 270 #define XPU_REG_DIFS_ADVANCE_ADDR (5*4) 271 #define XPU_REG_FORCE_IDLE_MISC_ADDR (6*4) 272 #define XPU_REG_RSSI_DB_CFG_ADDR (7*4) 273 #define XPU_REG_LBT_TH_ADDR (8*4) 274 #define XPU_REG_CSMA_DEBUG_ADDR (9*4) 275 #define XPU_REG_BB_RF_DELAY_ADDR (10*4) 276 #define XPU_REG_ACK_CTL_MAX_NUM_RETRANS_ADDR (11*4) 277 #define XPU_REG_AMPDU_ACTION_ADDR (12*4) 278 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4) 279 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4) 280 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) 281 #define XPU_REG_CSMA_CFG_ADDR (19*4) 282 283 #define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) 284 #define XPU_REG_SLICE_COUNT_START_ADDR (21*4) 285 #define XPU_REG_SLICE_COUNT_END_ADDR (22*4) 286 287 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4) 288 #define XPU_REG_FILTER_FLAG_ADDR (27*4) 289 #define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4) 290 #define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4) 291 #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) 292 #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) 293 294 #define XPU_REG_FC_DI_ADDR (34*4) 295 #define XPU_REG_ADDR1_LOW_ADDR (35*4) 296 #define XPU_REG_ADDR1_HIGH_ADDR (36*4) 297 #define XPU_REG_ADDR2_LOW_ADDR (37*4) 298 #define XPU_REG_ADDR2_HIGH_ADDR (38*4) 299 #define XPU_REG_ADDR3_LOW_ADDR (39*4) 300 #define XPU_REG_ADDR3_HIGH_ADDR (40*4) 301 302 #define XPU_REG_SC_LOW_ADDR (41*4) 303 #define XPU_REG_ADDR4_HIGH_ADDR (42*4) 304 #define XPU_REG_ADDR4_LOW_ADDR (43*4) 305 306 #define XPU_REG_TRX_STATUS_ADDR (50*4) 307 #define XPU_REG_TX_RESULT_ADDR (51*4) 308 309 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) 310 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) 311 312 #define XPU_REG_RSSI_HALF_DB_ADDR (60*4) 313 #define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4) 314 315 enum xpu_mode { 316 XPU_TEST = 0, 317 XPU_NORMAL, 318 }; 319 320 struct xpu_driver_api { 321 u32 (*hw_init)(enum xpu_mode mode); 322 323 u32 (*reg_read)(u32 reg); 324 void (*reg_write)(u32 reg, u32 value); 325 326 void (*XPU_REG_MULTI_RST_write)(u32 value); 327 u32 (*XPU_REG_MULTI_RST_read)(void); 328 329 void (*XPU_REG_SRC_SEL_write)(u32 value); 330 u32 (*XPU_REG_SRC_SEL_read)(void); 331 332 void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value); 333 u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void); 334 335 void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value); 336 u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void); 337 338 void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value); 339 u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void); 340 341 void (*XPU_REG_ACK_FC_FILTER_write)(u32 value); 342 u32 (*XPU_REG_ACK_FC_FILTER_read)(void); 343 344 void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value); 345 u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void); 346 347 void (*XPU_REG_FILTER_FLAG_write)(u32 value); 348 u32 (*XPU_REG_FILTER_FLAG_read)(void); 349 350 void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value); 351 u32 (*XPU_REG_MAC_ADDR_LOW_read)(void); 352 353 void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value); 354 u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void); 355 356 void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value); 357 u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void); 358 359 void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value); 360 u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void); 361 362 void (*XPU_REG_BAND_CHANNEL_write)(u32 value); 363 u32 (*XPU_REG_BAND_CHANNEL_read)(void); 364 365 void (*XPU_REG_DIFS_ADVANCE_write)(u32 value); 366 u32 (*XPU_REG_DIFS_ADVANCE_read)(void); 367 368 void (*XPU_REG_FORCE_IDLE_MISC_write)(u32 value); 369 u32 (*XPU_REG_FORCE_IDLE_MISC_read)(void); 370 371 u32 (*XPU_REG_TRX_STATUS_read)(void); 372 u32 (*XPU_REG_TX_RESULT_read)(void); 373 374 u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void); 375 u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void); 376 377 void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value); 378 void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value); 379 void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value); 380 381 u32 (*XPU_REG_FC_DI_read)(void); 382 u32 (*XPU_REG_ADDR1_LOW_read)(void); 383 u32 (*XPU_REG_ADDR1_HIGH_read)(void); 384 u32 (*XPU_REG_ADDR2_LOW_read)(void); 385 u32 (*XPU_REG_ADDR2_HIGH_read)(void); 386 387 void (*XPU_REG_LBT_TH_write)(u32 value); 388 u32 (*XPU_REG_LBT_TH_read)(void); 389 390 void (*XPU_REG_RSSI_DB_CFG_write)(u32 value); 391 u32 (*XPU_REG_RSSI_DB_CFG_read)(void); 392 393 void (*XPU_REG_CSMA_DEBUG_write)(u32 value); 394 u32 (*XPU_REG_CSMA_DEBUG_read)(void); 395 396 void (*XPU_REG_CSMA_CFG_write)(u32 value); 397 u32 (*XPU_REG_CSMA_CFG_read)(void); 398 399 void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value); 400 void (*XPU_REG_SLICE_COUNT_START_write)(u32 value); 401 void (*XPU_REG_SLICE_COUNT_END_write)(u32 value); 402 void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value); 403 void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value); 404 void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value); 405 406 u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void); 407 u32 (*XPU_REG_SLICE_COUNT_START_read)(void); 408 u32 (*XPU_REG_SLICE_COUNT_END_read)(void); 409 u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void); 410 u32 (*XPU_REG_SLICE_COUNT_START1_read)(void); 411 u32 (*XPU_REG_SLICE_COUNT_END1_read)(void); 412 413 void (*XPU_REG_BB_RF_DELAY_write)(u32 value); 414 415 void (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_write)(u32 value); 416 u32 (*XPU_REG_ACK_CTL_MAX_NUM_RETRANS_read)(void); 417 418 void (*XPU_REG_AMPDU_ACTION_write)(u32 value); 419 u32 (*XPU_REG_AMPDU_ACTION_read)(void); 420 421 void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr); 422 }; 423 424 // #endif 425