1*17cfeb0bSXianjun Jiao<!-- 2*17cfeb0bSXianjun JiaoAuthor: Xianjun jiao 3*17cfeb0bSXianjun JiaoSPDX-FileCopyrightText: 2019 UGent 4*17cfeb0bSXianjun JiaoSPDX-License-Identifier: AGPL-3.0-or-later 5*17cfeb0bSXianjun Jiao--> 6*17cfeb0bSXianjun Jiao 7*17cfeb0bSXianjun Jiao 8*17cfeb0bSXianjun JiaoCounter/statistics (number of TX packet, RX packet, etc.) in FPGA is offered via side channel register write/read. 9*17cfeb0bSXianjun Jiao 10*17cfeb0bSXianjun JiaoThe 1st step is alway loading the side channel kernel module: 11*17cfeb0bSXianjun Jiao``` 12*17cfeb0bSXianjun Jiaoinsmod side_ch.ko 13*17cfeb0bSXianjun Jiao``` 14*17cfeb0bSXianjun Jiao 15*17cfeb0bSXianjun JiaoThe register write command is: 16*17cfeb0bSXianjun Jiao``` 17*17cfeb0bSXianjun Jiao./side_ch_ctl whXdY 18*17cfeb0bSXianjun JiaoX -- register index 19*17cfeb0bSXianjun JiaoY -- decimal value to be written 20*17cfeb0bSXianjun Jiao./side_ch_ctl whXhY 21*17cfeb0bSXianjun JiaoX -- register index 22*17cfeb0bSXianjun JiaoY -- hex value to be written (useful for MAC address) 23*17cfeb0bSXianjun Jiao``` 24*17cfeb0bSXianjun JiaoWrite register 26~31 with arbitrary value to reset the corresponding counter to 0. 25*17cfeb0bSXianjun Jiao 26*17cfeb0bSXianjun JiaoThe register read command is: 27*17cfeb0bSXianjun Jiao``` 28*17cfeb0bSXianjun Jiao./side_ch_ctl rhX 29*17cfeb0bSXianjun JiaoX -- register index 30*17cfeb0bSXianjun Jiao``` 31*17cfeb0bSXianjun Jiao 32*17cfeb0bSXianjun Jiao## Register definition 33*17cfeb0bSXianjun Jiao 34*17cfeb0bSXianjun JiaoThe register 26~31 readback value represents the number of event happened. Each register has two event sources that can be selected via bit in register 19. 35*17cfeb0bSXianjun Jiao 36*17cfeb0bSXianjun Jiaoregister idx|source selection reg19|event 37*17cfeb0bSXianjun Jiao------------|----------------------|----------- 38*17cfeb0bSXianjun Jiao26 |reg19[0] == 0 |short_preamble_detected 39*17cfeb0bSXianjun Jiao26 |reg19[0] == 1 |phy_tx_start 40*17cfeb0bSXianjun Jiao27 |reg19[4] == 0 |long_preamble_detected 41*17cfeb0bSXianjun Jiao27 |reg19[4] == 1 |phy_tx_done 42*17cfeb0bSXianjun Jiao28 |reg19[8] == 0 |pkt_header_valid_strobe 43*17cfeb0bSXianjun Jiao28 |reg19[8] == 1 |rssi_above_th 44*17cfeb0bSXianjun Jiao29 |reg19[12] == 0 |pkt_header_valid_strobe&pkt_header_valid 45*17cfeb0bSXianjun Jiao29 |reg19[12] == 1 |gain_change 46*17cfeb0bSXianjun Jiao30 |reg19[16] == 0 |((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data 47*17cfeb0bSXianjun Jiao30 |reg19[16] == 1 |agc_lock 48*17cfeb0bSXianjun Jiao31 |reg19[20] == 0 |(((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data 49*17cfeb0bSXianjun Jiao31 |reg19[20] == 1 |tx_pkt_need_ack 50*17cfeb0bSXianjun Jiao 51*17cfeb0bSXianjun JiaoNote: fcs_in_strobe means decoding is done (not necessarily CRC is correct); fcs_ok 1 means CRC correct; fcs_ok 0 means CRC not correct. 52*17cfeb0bSXianjun Jiao 53*17cfeb0bSXianjun JiaoNote: addr2_match means addr2 matches to the register (addr2_target) value; pkt_for_me means addr1 matches self mac addr; is_data means the packet type is data. 54*17cfeb0bSXianjun Jiao 55*17cfeb0bSXianjun JiaoConfiguration register: 56*17cfeb0bSXianjun Jiao 57*17cfeb0bSXianjun Jiaoregister idx|meaning |note 58*17cfeb0bSXianjun Jiao------------|----------------------|----------- 59*17cfeb0bSXianjun Jiao7 |addr2 target value |fcs event always needs addr2 match 60*17cfeb0bSXianjun Jiao9 |threshold for event rssi_above_th|check auto_lbt_th in ad9361_rf_set_channel of sdr.c to estimate a proper value 61*17cfeb0bSXianjun Jiao 62*17cfeb0bSXianjun JiaoNote: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1 63*17cfeb0bSXianjun Jiao 64*17cfeb0bSXianjun JiaoNote: read register 37 of xpu for some addr2 captured by the receiver 65