117cfeb0bSXianjun Jiao<!-- 217cfeb0bSXianjun JiaoAuthor: Xianjun jiao 317cfeb0bSXianjun JiaoSPDX-FileCopyrightText: 2019 UGent 417cfeb0bSXianjun JiaoSPDX-License-Identifier: AGPL-3.0-or-later 517cfeb0bSXianjun Jiao--> 617cfeb0bSXianjun Jiao 717cfeb0bSXianjun Jiao 817cfeb0bSXianjun JiaoCounter/statistics (number of TX packet, RX packet, etc.) in FPGA is offered via side channel register write/read. 917cfeb0bSXianjun Jiao 1017cfeb0bSXianjun JiaoThe 1st step is alway loading the side channel kernel module: 1117cfeb0bSXianjun Jiao``` 1217cfeb0bSXianjun Jiaoinsmod side_ch.ko 1317cfeb0bSXianjun Jiao``` 1417cfeb0bSXianjun Jiao 1517cfeb0bSXianjun JiaoThe register write command is: 1617cfeb0bSXianjun Jiao``` 1717cfeb0bSXianjun Jiao./side_ch_ctl whXdY 1817cfeb0bSXianjun JiaoX -- register index 1917cfeb0bSXianjun JiaoY -- decimal value to be written 2017cfeb0bSXianjun Jiao./side_ch_ctl whXhY 2117cfeb0bSXianjun JiaoX -- register index 2217cfeb0bSXianjun JiaoY -- hex value to be written (useful for MAC address) 2317cfeb0bSXianjun Jiao``` 2417cfeb0bSXianjun JiaoWrite register 26~31 with arbitrary value to reset the corresponding counter to 0. 2517cfeb0bSXianjun Jiao 2617cfeb0bSXianjun JiaoThe register read command is: 2717cfeb0bSXianjun Jiao``` 2817cfeb0bSXianjun Jiao./side_ch_ctl rhX 2917cfeb0bSXianjun JiaoX -- register index 3017cfeb0bSXianjun Jiao``` 3117cfeb0bSXianjun Jiao 3217cfeb0bSXianjun Jiao## Register definition 3317cfeb0bSXianjun Jiao 3417cfeb0bSXianjun JiaoThe register 26~31 readback value represents the number of event happened. Each register has two event sources that can be selected via bit in register 19. 3517cfeb0bSXianjun Jiao 3617cfeb0bSXianjun Jiaoregister idx|source selection reg19|event 3717cfeb0bSXianjun Jiao------------|----------------------|----------- 3817cfeb0bSXianjun Jiao26 |reg19[0] == 0 |short_preamble_detected 3917cfeb0bSXianjun Jiao26 |reg19[0] == 1 |phy_tx_start 4017cfeb0bSXianjun Jiao27 |reg19[4] == 0 |long_preamble_detected 4117cfeb0bSXianjun Jiao27 |reg19[4] == 1 |phy_tx_done 4217cfeb0bSXianjun Jiao28 |reg19[8] == 0 |pkt_header_valid_strobe 4317cfeb0bSXianjun Jiao28 |reg19[8] == 1 |rssi_above_th 4417cfeb0bSXianjun Jiao29 |reg19[12] == 0 |pkt_header_valid_strobe&pkt_header_valid 4517cfeb0bSXianjun Jiao29 |reg19[12] == 1 |gain_change 4617cfeb0bSXianjun Jiao30 |reg19[16] == 0 |((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data 4717cfeb0bSXianjun Jiao30 |reg19[16] == 1 |agc_lock 4817cfeb0bSXianjun Jiao31 |reg19[20] == 0 |(((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data 4917cfeb0bSXianjun Jiao31 |reg19[20] == 1 |tx_pkt_need_ack 5017cfeb0bSXianjun Jiao 5117cfeb0bSXianjun JiaoNote: fcs_in_strobe means decoding is done (not necessarily CRC is correct); fcs_ok 1 means CRC correct; fcs_ok 0 means CRC not correct. 5217cfeb0bSXianjun Jiao 5317cfeb0bSXianjun JiaoNote: addr2_match means addr2 matches to the register (addr2_target) value; pkt_for_me means addr1 matches self mac addr; is_data means the packet type is data. 5417cfeb0bSXianjun Jiao 5517cfeb0bSXianjun JiaoConfiguration register: 5617cfeb0bSXianjun Jiao 5717cfeb0bSXianjun Jiaoregister idx|meaning |note 5817cfeb0bSXianjun Jiao------------|----------------------|----------- 5917cfeb0bSXianjun Jiao7 |addr2 target value |fcs event always needs addr2 match 6017cfeb0bSXianjun Jiao9 |threshold for event rssi_above_th|check auto_lbt_th in ad9361_rf_set_channel of sdr.c to estimate a proper value 6117cfeb0bSXianjun Jiao 6217cfeb0bSXianjun JiaoNote: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1 6317cfeb0bSXianjun Jiao 64*f6dab9cdSThijs HavingaNote: read register 62 of xpu for some addr2 captured by the receiver 65