1#include "macdefs.inc" 2 3 name OS_Core 4 5 COMMON INTVEC:CODE 6 7;******************************************************************** 8; 9; function: 10; description: Trap 0x10 vector used for context switch 11; Right now, all TRAPs to $1x are trated the same way 12; 13 org 50h 14 jr OSCtxSW 15 16 17;******************************************************************** 18; 19; function: 20; description: Timer 40 compare match interrupt used for system 21; tick interrupt 22; 23 org 0x220 24 jr OSTickIntr 25 26 org 0x0520 27 jr uarta1_int_r 28 29 RSEG CODE(1) 30 31 EXTERN rt_thread_switch_interrupt_flag 32 EXTERN rt_interrupt_from_thread 33 EXTERN rt_interrupt_to_thread 34 35 EXTERN rt_interrupt_enter 36 EXTERN rt_interrupt_leave 37 EXTERN rt_tick_increase 38 EXTERN uarta1_receive_handler 39 40 PUBLIC rt_hw_interrupt_disable 41 PUBLIC rt_hw_interrupt_enable 42 PUBLIC rt_hw_context_switch_to 43 PUBLIC OSCtxSW 44 PUBLIC OS_Restore_CPU_Context 45 46rt_hw_interrupt_disable: 47 stsr psw, r1 48 di 49 jmp [lp] 50 51rt_hw_interrupt_enable: 52 ldsr r1, psw 53 jmp [lp] 54 55OS_Restore_CPU_Context: 56 mov sp, ep 57 sld.w 4[ep], r2 58 sld.w 8[ep], r5 59 sld.w 12[ep],r6 60 sld.w 16[ep],r7 61 sld.w 20[ep],r8 62 sld.w 24[ep],r9 63 sld.w 28[ep],r10 64 sld.w 32[ep],r11 65 sld.w 36[ep],r12 66 sld.w 40[ep],r13 67 sld.w 44[ep],r14 68 sld.w 48[ep],r15 69 sld.w 52[ep],r16 70 71 ;See what was the latest interruption (trap or interrupt) 72 stsr ecr, r17 ;Move ecr to r17 73 mov 0x050,r1 74 cmp r1, r17 ;If latest break was due to TRAP, set EP 75 be _SetEP 76 77_ClrEP: 78 mov 0x20, r17 ;Set only ID 79 ldsr r17, psw 80 81 ;Restore caller address 82 sld.w 56[ep], r1 83 ldsr r1, EIPC 84 ;Restore PSW 85 sld.w 60[ep], r1 86 andi 0xffdf,r1,r1 87 ldsr r1, EIPSW 88 sld.w 0[ep], r1 89 dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} 90 91 ;Return from interrupt starts new task! 92 reti 93 94_SetEP: 95 mov 0x60, r17 ;Set both EIPC and ID bits 96 ldsr r17, psw 97 98 ;Restore caller address 99 sld.w 56[ep], r1 100 ldsr r1, EIPC 101 ;Restore PSW 102 sld.w 60[ep], r1 103 andi 0xffdf,r1,r1 104 ldsr r1, EIPSW 105 sld.w 0[ep], r1 106 dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} 107 108 ;Return from interrupt starts new task! 109 reti 110 111//rseg CODE:CODE 112//public rt_hw_context_switch_to 113rt_hw_context_switch_to: 114 ;Load stack pointer of the task to run 115 ld.w 0[r1], sp ;load sp from struct 116 117 ;Restore all Processor registers from stack and return from interrupt 118 jr OS_Restore_CPU_Context 119 120OSCtxSW: 121 SAVE_CPU_CTX ;Save all CPU registers 122 123 mov rt_interrupt_from_thread, r21 124 ld.w 0[r21], r21 125 st.w sp, 0[r21] 126 127 mov rt_interrupt_to_thread, r1 128 ld.w 0[r1], r1 129 ld.w 0[r1], sp 130 131 ;Restore all Processor registers from stack and return from interrupt 132 jr OS_Restore_CPU_Context 133 134rt_hw_context_switch_interrupt_do: 135 mov rt_thread_switch_interrupt_flag, r8 136 mov 0, r9 137 st.b r9, 0[r8] 138 139 mov rt_interrupt_from_thread, r21 140 ld.w 0[r21], r21 141 st.w sp, 0[r21] 142 143 mov rt_interrupt_to_thread, r1 144 ld.w 0[r1], r1 145 ld.w 0[r1], sp 146 jr OS_Restore_CPU_Context 147 148OSTickIntr: 149 SAVE_CPU_CTX ;Save current task's registers 150 jarl rt_interrupt_enter,lp 151 jarl rt_tick_increase,lp 152 jarl rt_interrupt_leave,lp 153 154 mov rt_thread_switch_interrupt_flag, r8 155 ld.w 0[r8],r9 156 cmp 1, r9 157 be rt_hw_context_switch_interrupt_do 158 159 jr OS_Restore_CPU_Context 160 161uarta1_int_r: 162 SAVE_CPU_CTX ;Save current task's registers 163 jarl rt_interrupt_enter,lp 164 jarl uarta1_receive_handler,lp 165 jarl rt_interrupt_leave,lp 166 167 mov rt_thread_switch_interrupt_flag, r8 168 ld.w 0[r8],r9 169 cmp 1, r9 170 be rt_hw_context_switch_interrupt_do 171 172 jr OS_Restore_CPU_Context 173 174 END 175