1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018/10/28 Bernard The unify RISC-V porting code. 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero #include <rthw.h> 12*10465441SEvalZero #include <rtthread.h> 13*10465441SEvalZero 14*10465441SEvalZero #include <encoding.h> 15*10465441SEvalZero #include <clint.h> 16*10465441SEvalZero #include <sysctl.h> 17*10465441SEvalZero 18*10465441SEvalZero static volatile unsigned long tick_cycles = 0; tick_isr(void)19*10465441SEvalZeroint tick_isr(void) 20*10465441SEvalZero { 21*10465441SEvalZero uint64_t core_id = current_coreid(); 22*10465441SEvalZero 23*10465441SEvalZero clint->mtimecmp[core_id] += tick_cycles; 24*10465441SEvalZero rt_tick_increase(); 25*10465441SEvalZero 26*10465441SEvalZero return 0; 27*10465441SEvalZero } 28*10465441SEvalZero 29*10465441SEvalZero /* Sets and enable the timer interrupt */ rt_hw_tick_init(void)30*10465441SEvalZeroint rt_hw_tick_init(void) 31*10465441SEvalZero { 32*10465441SEvalZero /* Read core id */ 33*10465441SEvalZero unsigned long core_id = current_coreid(); 34*10465441SEvalZero unsigned long interval = 1000/RT_TICK_PER_SECOND; 35*10465441SEvalZero 36*10465441SEvalZero /* Clear the Machine-Timer bit in MIE */ 37*10465441SEvalZero clear_csr(mie, MIP_MTIP); 38*10465441SEvalZero 39*10465441SEvalZero /* calculate the tick cycles */ 40*10465441SEvalZero tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1; 41*10465441SEvalZero /* Set mtimecmp by core id */ 42*10465441SEvalZero clint->mtimecmp[core_id] = clint->mtime + tick_cycles; 43*10465441SEvalZero 44*10465441SEvalZero /* Enable the Machine-Timer bit in MIE */ 45*10465441SEvalZero set_csr(mie, MIP_MTIP); 46*10465441SEvalZero 47*10465441SEvalZero return 0; 48*10465441SEvalZero } 49