xref: /nrf52832-nimble/rt-thread/libcpu/risc-v/k210/tick.c (revision 104654410c56c573564690304ae786df310c91fc)
1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018/10/28     Bernard      The unify RISC-V porting code.
9  */
10 
11 #include <rthw.h>
12 #include <rtthread.h>
13 
14 #include <encoding.h>
15 #include <clint.h>
16 #include <sysctl.h>
17 
18 static volatile unsigned long tick_cycles = 0;
tick_isr(void)19 int tick_isr(void)
20 {
21     uint64_t core_id = current_coreid();
22 
23     clint->mtimecmp[core_id] += tick_cycles;
24     rt_tick_increase();
25 
26     return 0;
27 }
28 
29 /* Sets and enable the timer interrupt */
rt_hw_tick_init(void)30 int rt_hw_tick_init(void)
31 {
32     /* Read core id */
33     unsigned long core_id = current_coreid();
34     unsigned long interval = 1000/RT_TICK_PER_SECOND;
35 
36     /* Clear the Machine-Timer bit in MIE */
37     clear_csr(mie, MIP_MTIP);
38 
39     /* calculate the tick cycles */
40     tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
41     /* Set mtimecmp by core id */
42     clint->mtimecmp[core_id] = clint->mtime + tick_cycles;
43 
44     /* Enable the Machine-Timer bit in MIE */
45     set_csr(mie, MIP_MTIP);
46 
47     return 0;
48 }
49