1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018/10/01 Bernard The first version 9*10465441SEvalZero * 2018/12/27 Jesven Add SMP support 10*10465441SEvalZero */ 11*10465441SEvalZero 12*10465441SEvalZero#define MSTATUS_FS 0x00006000U /* initial state of FPU */ 13*10465441SEvalZero#include <cpuport.h> 14*10465441SEvalZero 15*10465441SEvalZero .global _start 16*10465441SEvalZero .section ".start", "ax" 17*10465441SEvalZero_start: 18*10465441SEvalZero j 1f 19*10465441SEvalZero .word 0xdeadbeef 20*10465441SEvalZero .align 3 21*10465441SEvalZero .global g_wake_up 22*10465441SEvalZero g_wake_up: 23*10465441SEvalZero .dword 1 24*10465441SEvalZero .dword 0 25*10465441SEvalZero1: 26*10465441SEvalZero csrw mideleg, 0 27*10465441SEvalZero csrw medeleg, 0 28*10465441SEvalZero csrw mie, 0 29*10465441SEvalZero csrw mip, 0 30*10465441SEvalZero la t0, trap_entry 31*10465441SEvalZero csrw mtvec, t0 32*10465441SEvalZero 33*10465441SEvalZero li x1, 0 34*10465441SEvalZero li x2, 0 35*10465441SEvalZero li x3, 0 36*10465441SEvalZero li x4, 0 37*10465441SEvalZero li x5, 0 38*10465441SEvalZero li x6, 0 39*10465441SEvalZero li x7, 0 40*10465441SEvalZero li x8, 0 41*10465441SEvalZero li x9, 0 42*10465441SEvalZero li x10,0 43*10465441SEvalZero li x11,0 44*10465441SEvalZero li x12,0 45*10465441SEvalZero li x13,0 46*10465441SEvalZero li x14,0 47*10465441SEvalZero li x15,0 48*10465441SEvalZero li x16,0 49*10465441SEvalZero li x17,0 50*10465441SEvalZero li x18,0 51*10465441SEvalZero li x19,0 52*10465441SEvalZero li x20,0 53*10465441SEvalZero li x21,0 54*10465441SEvalZero li x22,0 55*10465441SEvalZero li x23,0 56*10465441SEvalZero li x24,0 57*10465441SEvalZero li x25,0 58*10465441SEvalZero li x26,0 59*10465441SEvalZero li x27,0 60*10465441SEvalZero li x28,0 61*10465441SEvalZero li x29,0 62*10465441SEvalZero li x30,0 63*10465441SEvalZero li x31,0 64*10465441SEvalZero 65*10465441SEvalZero /* set to initial state of FPU and disable interrupt */ 66*10465441SEvalZero li t0, MSTATUS_FS 67*10465441SEvalZero csrs mstatus, t0 68*10465441SEvalZero 69*10465441SEvalZero fssr x0 70*10465441SEvalZero fmv.d.x f0, x0 71*10465441SEvalZero fmv.d.x f1, x0 72*10465441SEvalZero fmv.d.x f2, x0 73*10465441SEvalZero fmv.d.x f3, x0 74*10465441SEvalZero fmv.d.x f4, x0 75*10465441SEvalZero fmv.d.x f5, x0 76*10465441SEvalZero fmv.d.x f6, x0 77*10465441SEvalZero fmv.d.x f7, x0 78*10465441SEvalZero fmv.d.x f8, x0 79*10465441SEvalZero fmv.d.x f9, x0 80*10465441SEvalZero fmv.d.x f10,x0 81*10465441SEvalZero fmv.d.x f11,x0 82*10465441SEvalZero fmv.d.x f12,x0 83*10465441SEvalZero fmv.d.x f13,x0 84*10465441SEvalZero fmv.d.x f14,x0 85*10465441SEvalZero fmv.d.x f15,x0 86*10465441SEvalZero fmv.d.x f16,x0 87*10465441SEvalZero fmv.d.x f17,x0 88*10465441SEvalZero fmv.d.x f18,x0 89*10465441SEvalZero fmv.d.x f19,x0 90*10465441SEvalZero fmv.d.x f20,x0 91*10465441SEvalZero fmv.d.x f21,x0 92*10465441SEvalZero fmv.d.x f22,x0 93*10465441SEvalZero fmv.d.x f23,x0 94*10465441SEvalZero fmv.d.x f24,x0 95*10465441SEvalZero fmv.d.x f25,x0 96*10465441SEvalZero fmv.d.x f26,x0 97*10465441SEvalZero fmv.d.x f27,x0 98*10465441SEvalZero fmv.d.x f28,x0 99*10465441SEvalZero fmv.d.x f29,x0 100*10465441SEvalZero fmv.d.x f30,x0 101*10465441SEvalZero fmv.d.x f31,x0 102*10465441SEvalZero 103*10465441SEvalZero.option push 104*10465441SEvalZero.option norelax 105*10465441SEvalZero la gp, __global_pointer$ 106*10465441SEvalZero.option pop 107*10465441SEvalZero 108*10465441SEvalZero /* get cpu id */ 109*10465441SEvalZero csrr a0, mhartid 110*10465441SEvalZero 111*10465441SEvalZero la sp, __stack_start__ 112*10465441SEvalZero addi t1, a0, 1 113*10465441SEvalZero li t2, __STACKSIZE__ 114*10465441SEvalZero mul t1, t1, t2 115*10465441SEvalZero add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ 116*10465441SEvalZero 117*10465441SEvalZero /* other cpu core, jump to cpu entry directly */ 118*10465441SEvalZero bnez a0, secondary_cpu_entry 119*10465441SEvalZero j primary_cpu_entry 120*10465441SEvalZero 121*10465441SEvalZerosecondary_cpu_entry: 122*10465441SEvalZero#ifdef RT_USING_SMP 123*10465441SEvalZero la a0, secondary_boot_flag 124*10465441SEvalZero ld a0, 0(a0) 125*10465441SEvalZero li a1, 0xa55a 126*10465441SEvalZero beq a0, a1, secondary_cpu_c_start 127*10465441SEvalZero#endif 128*10465441SEvalZero j secondary_cpu_entry 129*10465441SEvalZero 130*10465441SEvalZero#ifdef RT_USING_SMP 131*10465441SEvalZero.data 132*10465441SEvalZero.global secondary_boot_flag 133*10465441SEvalZero.align 3 134*10465441SEvalZerosecondary_boot_flag: 135*10465441SEvalZero .dword 0 136*10465441SEvalZero#endif 137