1/* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018/10/01 Bernard The first version 9 * 2018/12/27 Jesven Add SMP support 10 */ 11 12#define MSTATUS_FS 0x00006000U /* initial state of FPU */ 13#include <cpuport.h> 14 15 .global _start 16 .section ".start", "ax" 17_start: 18 j 1f 19 .word 0xdeadbeef 20 .align 3 21 .global g_wake_up 22 g_wake_up: 23 .dword 1 24 .dword 0 251: 26 csrw mideleg, 0 27 csrw medeleg, 0 28 csrw mie, 0 29 csrw mip, 0 30 la t0, trap_entry 31 csrw mtvec, t0 32 33 li x1, 0 34 li x2, 0 35 li x3, 0 36 li x4, 0 37 li x5, 0 38 li x6, 0 39 li x7, 0 40 li x8, 0 41 li x9, 0 42 li x10,0 43 li x11,0 44 li x12,0 45 li x13,0 46 li x14,0 47 li x15,0 48 li x16,0 49 li x17,0 50 li x18,0 51 li x19,0 52 li x20,0 53 li x21,0 54 li x22,0 55 li x23,0 56 li x24,0 57 li x25,0 58 li x26,0 59 li x27,0 60 li x28,0 61 li x29,0 62 li x30,0 63 li x31,0 64 65 /* set to initial state of FPU and disable interrupt */ 66 li t0, MSTATUS_FS 67 csrs mstatus, t0 68 69 fssr x0 70 fmv.d.x f0, x0 71 fmv.d.x f1, x0 72 fmv.d.x f2, x0 73 fmv.d.x f3, x0 74 fmv.d.x f4, x0 75 fmv.d.x f5, x0 76 fmv.d.x f6, x0 77 fmv.d.x f7, x0 78 fmv.d.x f8, x0 79 fmv.d.x f9, x0 80 fmv.d.x f10,x0 81 fmv.d.x f11,x0 82 fmv.d.x f12,x0 83 fmv.d.x f13,x0 84 fmv.d.x f14,x0 85 fmv.d.x f15,x0 86 fmv.d.x f16,x0 87 fmv.d.x f17,x0 88 fmv.d.x f18,x0 89 fmv.d.x f19,x0 90 fmv.d.x f20,x0 91 fmv.d.x f21,x0 92 fmv.d.x f22,x0 93 fmv.d.x f23,x0 94 fmv.d.x f24,x0 95 fmv.d.x f25,x0 96 fmv.d.x f26,x0 97 fmv.d.x f27,x0 98 fmv.d.x f28,x0 99 fmv.d.x f29,x0 100 fmv.d.x f30,x0 101 fmv.d.x f31,x0 102 103.option push 104.option norelax 105 la gp, __global_pointer$ 106.option pop 107 108 /* get cpu id */ 109 csrr a0, mhartid 110 111 la sp, __stack_start__ 112 addi t1, a0, 1 113 li t2, __STACKSIZE__ 114 mul t1, t1, t2 115 add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ 116 117 /* other cpu core, jump to cpu entry directly */ 118 bnez a0, secondary_cpu_entry 119 j primary_cpu_entry 120 121secondary_cpu_entry: 122#ifdef RT_USING_SMP 123 la a0, secondary_boot_flag 124 ld a0, 0(a0) 125 li a1, 0xa55a 126 beq a0, a1, secondary_cpu_c_start 127#endif 128 j secondary_cpu_entry 129 130#ifdef RT_USING_SMP 131.data 132.global secondary_boot_flag 133.align 3 134secondary_boot_flag: 135 .dword 0 136#endif 137