1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018/10/02 Bernard The first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero#include "cpuport.h" 12*10465441SEvalZero 13*10465441SEvalZero .section .text.entry 14*10465441SEvalZero .align 2 15*10465441SEvalZero .global trap_entry 16*10465441SEvalZerotrap_entry: 17*10465441SEvalZero 18*10465441SEvalZero /* save all from thread context */ 19*10465441SEvalZero addi sp, sp, -32 * REGBYTES 20*10465441SEvalZero 21*10465441SEvalZero STORE x1, 1 * REGBYTES(sp) 22*10465441SEvalZero li t0, 0x80 23*10465441SEvalZero STORE t0, 2 * REGBYTES(sp) 24*10465441SEvalZero 25*10465441SEvalZero STORE x4, 4 * REGBYTES(sp) 26*10465441SEvalZero STORE x5, 5 * REGBYTES(sp) 27*10465441SEvalZero STORE x6, 6 * REGBYTES(sp) 28*10465441SEvalZero STORE x7, 7 * REGBYTES(sp) 29*10465441SEvalZero STORE x8, 8 * REGBYTES(sp) 30*10465441SEvalZero STORE x9, 9 * REGBYTES(sp) 31*10465441SEvalZero STORE x10, 10 * REGBYTES(sp) 32*10465441SEvalZero STORE x11, 11 * REGBYTES(sp) 33*10465441SEvalZero STORE x12, 12 * REGBYTES(sp) 34*10465441SEvalZero STORE x13, 13 * REGBYTES(sp) 35*10465441SEvalZero STORE x14, 14 * REGBYTES(sp) 36*10465441SEvalZero STORE x15, 15 * REGBYTES(sp) 37*10465441SEvalZero STORE x16, 16 * REGBYTES(sp) 38*10465441SEvalZero STORE x17, 17 * REGBYTES(sp) 39*10465441SEvalZero STORE x18, 18 * REGBYTES(sp) 40*10465441SEvalZero STORE x19, 19 * REGBYTES(sp) 41*10465441SEvalZero STORE x20, 20 * REGBYTES(sp) 42*10465441SEvalZero STORE x21, 21 * REGBYTES(sp) 43*10465441SEvalZero STORE x22, 22 * REGBYTES(sp) 44*10465441SEvalZero STORE x23, 23 * REGBYTES(sp) 45*10465441SEvalZero STORE x24, 24 * REGBYTES(sp) 46*10465441SEvalZero STORE x25, 25 * REGBYTES(sp) 47*10465441SEvalZero STORE x26, 26 * REGBYTES(sp) 48*10465441SEvalZero STORE x27, 27 * REGBYTES(sp) 49*10465441SEvalZero STORE x28, 28 * REGBYTES(sp) 50*10465441SEvalZero STORE x29, 29 * REGBYTES(sp) 51*10465441SEvalZero STORE x30, 30 * REGBYTES(sp) 52*10465441SEvalZero STORE x31, 31 * REGBYTES(sp) 53*10465441SEvalZero 54*10465441SEvalZero /* save break thread stack to s0 */ 55*10465441SEvalZero move s0, sp 56*10465441SEvalZero /* switch to interrupt stack */ 57*10465441SEvalZero la sp, _sp 58*10465441SEvalZero 59*10465441SEvalZero /* interrupt handle */ 60*10465441SEvalZero call rt_interrupt_enter 61*10465441SEvalZero csrr a0, mcause 62*10465441SEvalZero csrr a1, mepc 63*10465441SEvalZero mv a2, sp 64*10465441SEvalZero call handle_trap 65*10465441SEvalZero call rt_interrupt_leave 66*10465441SEvalZero 67*10465441SEvalZero /* switch to from_thread stack */ 68*10465441SEvalZero move sp, s0 69*10465441SEvalZero 70*10465441SEvalZero /* need to switch new thread */ 71*10465441SEvalZero la s0, rt_thread_switch_interrupt_flag 72*10465441SEvalZero lw s2, 0(s0) 73*10465441SEvalZero beqz s2, spurious_interrupt 74*10465441SEvalZero sw zero, 0(s0) 75*10465441SEvalZero 76*10465441SEvalZero csrr a0, mepc 77*10465441SEvalZero STORE a0, 0 * REGBYTES(sp) 78*10465441SEvalZero 79*10465441SEvalZero la s0, rt_interrupt_from_thread 80*10465441SEvalZero LOAD s1, 0(s0) 81*10465441SEvalZero STORE sp, 0(s1) 82*10465441SEvalZero 83*10465441SEvalZero la s0, rt_interrupt_to_thread 84*10465441SEvalZero LOAD s1, 0(s0) 85*10465441SEvalZero LOAD sp, 0(s1) 86*10465441SEvalZero 87*10465441SEvalZero LOAD a0, 0 * REGBYTES(sp) 88*10465441SEvalZero csrw mepc, a0 89*10465441SEvalZero 90*10465441SEvalZerospurious_interrupt: 91*10465441SEvalZero LOAD x1, 1 * REGBYTES(sp) 92*10465441SEvalZero 93*10465441SEvalZero /* Remain in M-mode after mret */ 94*10465441SEvalZero li t0, 0x00001800 95*10465441SEvalZero csrs mstatus, t0 96*10465441SEvalZero LOAD t0, 2 * REGBYTES(sp) 97*10465441SEvalZero csrs mstatus, t0 98*10465441SEvalZero 99*10465441SEvalZero LOAD x4, 4 * REGBYTES(sp) 100*10465441SEvalZero LOAD x5, 5 * REGBYTES(sp) 101*10465441SEvalZero LOAD x6, 6 * REGBYTES(sp) 102*10465441SEvalZero LOAD x7, 7 * REGBYTES(sp) 103*10465441SEvalZero LOAD x8, 8 * REGBYTES(sp) 104*10465441SEvalZero LOAD x9, 9 * REGBYTES(sp) 105*10465441SEvalZero LOAD x10, 10 * REGBYTES(sp) 106*10465441SEvalZero LOAD x11, 11 * REGBYTES(sp) 107*10465441SEvalZero LOAD x12, 12 * REGBYTES(sp) 108*10465441SEvalZero LOAD x13, 13 * REGBYTES(sp) 109*10465441SEvalZero LOAD x14, 14 * REGBYTES(sp) 110*10465441SEvalZero LOAD x15, 15 * REGBYTES(sp) 111*10465441SEvalZero LOAD x16, 16 * REGBYTES(sp) 112*10465441SEvalZero LOAD x17, 17 * REGBYTES(sp) 113*10465441SEvalZero LOAD x18, 18 * REGBYTES(sp) 114*10465441SEvalZero LOAD x19, 19 * REGBYTES(sp) 115*10465441SEvalZero LOAD x20, 20 * REGBYTES(sp) 116*10465441SEvalZero LOAD x21, 21 * REGBYTES(sp) 117*10465441SEvalZero LOAD x22, 22 * REGBYTES(sp) 118*10465441SEvalZero LOAD x23, 23 * REGBYTES(sp) 119*10465441SEvalZero LOAD x24, 24 * REGBYTES(sp) 120*10465441SEvalZero LOAD x25, 25 * REGBYTES(sp) 121*10465441SEvalZero LOAD x26, 26 * REGBYTES(sp) 122*10465441SEvalZero LOAD x27, 27 * REGBYTES(sp) 123*10465441SEvalZero LOAD x28, 28 * REGBYTES(sp) 124*10465441SEvalZero LOAD x29, 29 * REGBYTES(sp) 125*10465441SEvalZero LOAD x30, 30 * REGBYTES(sp) 126*10465441SEvalZero LOAD x31, 31 * REGBYTES(sp) 127*10465441SEvalZero 128*10465441SEvalZero addi sp, sp, 32 * REGBYTES 129*10465441SEvalZero mret 130