1/* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018/10/02 Bernard The first version 9 */ 10 11#include "cpuport.h" 12 13 .section .text.entry 14 .align 2 15 .global trap_entry 16trap_entry: 17 18 /* save all from thread context */ 19 addi sp, sp, -32 * REGBYTES 20 21 STORE x1, 1 * REGBYTES(sp) 22 li t0, 0x80 23 STORE t0, 2 * REGBYTES(sp) 24 25 STORE x4, 4 * REGBYTES(sp) 26 STORE x5, 5 * REGBYTES(sp) 27 STORE x6, 6 * REGBYTES(sp) 28 STORE x7, 7 * REGBYTES(sp) 29 STORE x8, 8 * REGBYTES(sp) 30 STORE x9, 9 * REGBYTES(sp) 31 STORE x10, 10 * REGBYTES(sp) 32 STORE x11, 11 * REGBYTES(sp) 33 STORE x12, 12 * REGBYTES(sp) 34 STORE x13, 13 * REGBYTES(sp) 35 STORE x14, 14 * REGBYTES(sp) 36 STORE x15, 15 * REGBYTES(sp) 37 STORE x16, 16 * REGBYTES(sp) 38 STORE x17, 17 * REGBYTES(sp) 39 STORE x18, 18 * REGBYTES(sp) 40 STORE x19, 19 * REGBYTES(sp) 41 STORE x20, 20 * REGBYTES(sp) 42 STORE x21, 21 * REGBYTES(sp) 43 STORE x22, 22 * REGBYTES(sp) 44 STORE x23, 23 * REGBYTES(sp) 45 STORE x24, 24 * REGBYTES(sp) 46 STORE x25, 25 * REGBYTES(sp) 47 STORE x26, 26 * REGBYTES(sp) 48 STORE x27, 27 * REGBYTES(sp) 49 STORE x28, 28 * REGBYTES(sp) 50 STORE x29, 29 * REGBYTES(sp) 51 STORE x30, 30 * REGBYTES(sp) 52 STORE x31, 31 * REGBYTES(sp) 53 54 /* save break thread stack to s0 */ 55 move s0, sp 56 /* switch to interrupt stack */ 57 la sp, _sp 58 59 /* interrupt handle */ 60 call rt_interrupt_enter 61 csrr a0, mcause 62 csrr a1, mepc 63 mv a2, sp 64 call handle_trap 65 call rt_interrupt_leave 66 67 /* switch to from_thread stack */ 68 move sp, s0 69 70 /* need to switch new thread */ 71 la s0, rt_thread_switch_interrupt_flag 72 lw s2, 0(s0) 73 beqz s2, spurious_interrupt 74 sw zero, 0(s0) 75 76 csrr a0, mepc 77 STORE a0, 0 * REGBYTES(sp) 78 79 la s0, rt_interrupt_from_thread 80 LOAD s1, 0(s0) 81 STORE sp, 0(s1) 82 83 la s0, rt_interrupt_to_thread 84 LOAD s1, 0(s0) 85 LOAD sp, 0(s1) 86 87 LOAD a0, 0 * REGBYTES(sp) 88 csrw mepc, a0 89 90spurious_interrupt: 91 LOAD x1, 1 * REGBYTES(sp) 92 93 /* Remain in M-mode after mret */ 94 li t0, 0x00001800 95 csrs mstatus, t0 96 LOAD t0, 2 * REGBYTES(sp) 97 csrs mstatus, t0 98 99 LOAD x4, 4 * REGBYTES(sp) 100 LOAD x5, 5 * REGBYTES(sp) 101 LOAD x6, 6 * REGBYTES(sp) 102 LOAD x7, 7 * REGBYTES(sp) 103 LOAD x8, 8 * REGBYTES(sp) 104 LOAD x9, 9 * REGBYTES(sp) 105 LOAD x10, 10 * REGBYTES(sp) 106 LOAD x11, 11 * REGBYTES(sp) 107 LOAD x12, 12 * REGBYTES(sp) 108 LOAD x13, 13 * REGBYTES(sp) 109 LOAD x14, 14 * REGBYTES(sp) 110 LOAD x15, 15 * REGBYTES(sp) 111 LOAD x16, 16 * REGBYTES(sp) 112 LOAD x17, 17 * REGBYTES(sp) 113 LOAD x18, 18 * REGBYTES(sp) 114 LOAD x19, 19 * REGBYTES(sp) 115 LOAD x20, 20 * REGBYTES(sp) 116 LOAD x21, 21 * REGBYTES(sp) 117 LOAD x22, 22 * REGBYTES(sp) 118 LOAD x23, 23 * REGBYTES(sp) 119 LOAD x24, 24 * REGBYTES(sp) 120 LOAD x25, 25 * REGBYTES(sp) 121 LOAD x26, 26 * REGBYTES(sp) 122 LOAD x27, 27 * REGBYTES(sp) 123 LOAD x28, 28 * REGBYTES(sp) 124 LOAD x29, 29 * REGBYTES(sp) 125 LOAD x30, 30 * REGBYTES(sp) 126 LOAD x31, 31 * REGBYTES(sp) 127 128 addi sp, sp, 32 * REGBYTES 129 mret 130