1#define L1_CACHE_SHIFT 5 2#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 3#define DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ 4 5/* 6 * Flush instruction cache. 7 */ 8 .globl invalidate_icache 9invalidate_icache: 10 iccci r0,r0 11 isync 12 blr 13 14/* 15 * Write any modified data cache blocks out to memory 16 * and invalidate the corresponding instruction cache blocks. 17 * 18 * flush_icache_range(unsigned long start, unsigned long stop) 19 */ 20 .globl flush_icache_range 21flush_icache_range: 22 li r5,L1_CACHE_BYTES-1 23 andc r3,r3,r5 24 subf r4,r3,r4 25 add r4,r4,r5 26 srwi. r4,r4,L1_CACHE_SHIFT 27 beqlr 28 mtctr r4 29 mr r6,r3 301: dcbst 0,r3 31 addi r3,r3,L1_CACHE_BYTES 32 bdnz 1b 33 sync /* wait for dcbst's to get to ram */ 34 mtctr r4 352: icbi 0,r6 36 addi r6,r6,L1_CACHE_BYTES 37 bdnz 2b 38 sync /* additional sync needed on g4 */ 39 isync 40 blr 41 42/* 43 * Write any modified data cache blocks out to memory. 44 * Does not invalidate the corresponding cache lines (especially for 45 * any corresponding instruction cache). 46 * 47 * clean_dcache_range(unsigned long start, unsigned long stop) 48 */ 49 .globl clean_dcache_range 50clean_dcache_range: 51 li r5,L1_CACHE_BYTES-1 52 andc r3,r3,r5 53 subf r4,r3,r4 54 add r4,r4,r5 55 srwi. r4,r4,L1_CACHE_SHIFT 56 beqlr 57 mtctr r4 58 591: dcbst 0,r3 60 addi r3,r3,L1_CACHE_BYTES 61 bdnz 1b 62 sync /* wait for dcbst's to get to ram */ 63 blr 64 65/* 66 * Write any modified data cache blocks out to memory and invalidate them. 67 * Does not invalidate the corresponding instruction cache blocks. 68 * 69 * flush_dcache_range(unsigned long start, unsigned long stop) 70 */ 71 .globl flush_dcache_range 72flush_dcache_range: 73 li r5,L1_CACHE_BYTES-1 74 andc r3,r3,r5 75 subf r4,r3,r4 76 add r4,r4,r5 77 srwi. r4,r4,L1_CACHE_SHIFT 78 beqlr 79 mtctr r4 80 811: dcbf 0,r3 82 addi r3,r3,L1_CACHE_BYTES 83 bdnz 1b 84 sync /* wait for dcbst's to get to ram */ 85 blr 86 87/* 88 * Like above, but invalidate the D-cache. This is used by the 8xx 89 * to invalidate the cache so the PPC core doesn't get stale data 90 * from the CPM (no cache snooping here :-). 91 * 92 * invalidate_dcache_range(unsigned long start, unsigned long stop) 93 */ 94 .globl invalidate_dcache_range 95invalidate_dcache_range: 96 li r5,L1_CACHE_BYTES-1 97 andc r3,r3,r5 98 subf r4,r3,r4 99 add r4,r4,r5 100 srwi. r4,r4,L1_CACHE_SHIFT 101 beqlr 102 mtctr r4 103 1041: dcbi 0,r3 105 addi r3,r3,L1_CACHE_BYTES 106 bdnz 1b 107 sync /* wait for dcbi's to get to ram */ 108 blr 109 110/* 111 * 40x cores have 8K or 16K dcache and 32 byte line size. 112 * 44x has a 32K dcache and 32 byte line size. 113 * 8xx has 1, 2, 4, 8K variants. 114 * For now, cover the worst case of the 44x. 115 * Must be called with external interrupts disabled. 116 */ 117#define CACHE_NWAYS 64 118#define CACHE_NLINES 32 119 120 .globl flush_dcache 121flush_dcache: 122 li r4,(2 * CACHE_NWAYS * CACHE_NLINES) 123 mtctr r4 124 lis r5,0 1251: lwz r3,0(r5) /* Load one word from every line */ 126 addi r5,r5,L1_CACHE_BYTES 127 bdnz 1b 128 sync 129 blr 130 131 .globl invalidate_dcache 132invalidate_dcache: 133 addi r6,0,0x0000 /* clear GPR 6 */ 134 /* Do loop for # of dcache congruence classes. */ 135 lis r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */ 136 ori r7,r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@l 137 /* NOTE: dccci invalidates both */ 138 mtctr r7 /* ways in the D cache */ 139dcloop: 140 dccci 0,r6 /* invalidate line */ 141 addi r6,r6,L1_CACHE_BYTES /* bump to next line */ 142 bdnz dcloop 143 sync 144 blr 145 146/* 147 * Cache functions. 148 * 149 * Icache-related functions are used in POST framework. 150 */ 151 .globl icache_enable 152icache_enable: 153 mflr r8 154 bl invalidate_icache 155 mtlr r8 156 isync 157 addis r3,r0, 0xc000 /* set bit 0 */ 158 mticcr r3 159 blr 160 161 .globl icache_disable 162icache_disable: 163 addis r3,r0, 0x0000 /* clear bit 0 */ 164 mticcr r3 165 isync 166 blr 167 168 .globl icache_status 169icache_status: 170 mficcr r3 171 srwi r3, r3, 31 /* >>31 => select bit 0 */ 172 blr 173 174 .globl dcache_enable 175dcache_enable: 176 mflr r8 177 bl invalidate_dcache 178 mtlr r8 179 isync 180 addis r3,r0, 0x8000 /* set bit 0 */ 181 mtdccr r3 182 blr 183 184 .globl dcache_disable 185dcache_disable: 186 mflr r8 187 bl flush_dcache 188 mtlr r8 189 addis r3,r0, 0x0000 /* clear bit 0 */ 190 mtdccr r3 191 blr 192 193 .globl dcache_status 194dcache_status: 195 mfdccr r3 196 srwi r3, r3, 31 /* >>31 => select bit 0 */ 197 blr 198