1*10465441SEvalZero/* 2*10465441SEvalZero * File : start_gcc.S 3*10465441SEvalZero * Change Logs: 4*10465441SEvalZero * Date Author Notes 5*10465441SEvalZero * 2010-05-17 swkyer first version 6*10465441SEvalZero * 2010-09-04 bernard porting to Jz47xx 7*10465441SEvalZero */ 8*10465441SEvalZero 9*10465441SEvalZero#include "../common/mips.inc" 10*10465441SEvalZero#include "../common/stackframe.h" 11*10465441SEvalZero#include "stack.h" 12*10465441SEvalZero 13*10465441SEvalZero .section ".start", "ax" 14*10465441SEvalZero .set noreorder 15*10465441SEvalZero 16*10465441SEvalZero /* the program entry */ 17*10465441SEvalZero .globl _start 18*10465441SEvalZero_start: 19*10465441SEvalZero .set noreorder 20*10465441SEvalZero la ra, _start 21*10465441SEvalZero 22*10465441SEvalZero li t1, 0x00800000 23*10465441SEvalZero mtc0 t1, CP0_CAUSE 24*10465441SEvalZero 25*10465441SEvalZero /* init cp0 registers. */ 26*10465441SEvalZero li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ 27*10465441SEvalZero mtc0 t0, CP0_STATUS 28*10465441SEvalZero 29*10465441SEvalZero /* setup stack pointer */ 30*10465441SEvalZero li sp, SYSTEM_STACK 31*10465441SEvalZero la gp, _gp 32*10465441SEvalZero 33*10465441SEvalZero /* init caches, assumes a 4way * 128set * 32byte I/D cache */ 34*10465441SEvalZero mtc0 zero, CP0_TAGLO /* TAGLO reg */ 35*10465441SEvalZero mtc0 zero, CP0_TAGHI /* TAGHI reg */ 36*10465441SEvalZero li t0, 3 /* enable cache for kseg0 accesses */ 37*10465441SEvalZero mtc0 t0, CP0_CONFIG /* CONFIG reg */ 38*10465441SEvalZero la t0, 0x80000000 /* an idx op should use an unmappable address */ 39*10465441SEvalZero ori t1, t0, 0x4000 /* 16kB cache */ 40*10465441SEvalZero 41*10465441SEvalZero_cache_loop: 42*10465441SEvalZero cache 0x8, 0(t0) /* index store icache tag */ 43*10465441SEvalZero cache 0x9, 0(t0) /* index store dcache tag */ 44*10465441SEvalZero bne t0, t1, _cache_loop 45*10465441SEvalZero addiu t0, t0, 0x20 /* 32 bytes per cache line */ 46*10465441SEvalZero nop 47*10465441SEvalZero 48*10465441SEvalZero /* invalidate BTB */ 49*10465441SEvalZero mfc0 t0, CP0_CONFIG 50*10465441SEvalZero nop 51*10465441SEvalZero ori t0, 2 52*10465441SEvalZero mtc0 t0, CP0_CONFIG 53*10465441SEvalZero nop 54*10465441SEvalZero 55*10465441SEvalZero /* copy IRAM section */ 56*10465441SEvalZero la t0, _iramcopy 57*10465441SEvalZero la t1, _iramstart 58*10465441SEvalZero la t2, _iramend 59*10465441SEvalZero_iram_loop: 60*10465441SEvalZero lw t3, 0(t0) 61*10465441SEvalZero sw t3, 0(t1) 62*10465441SEvalZero addiu t1, 4 63*10465441SEvalZero bne t1, t2, _iram_loop 64*10465441SEvalZero addiu t0, 4 65*10465441SEvalZero /* clear bss */ 66*10465441SEvalZero la t0, __bss_start 67*10465441SEvalZero la t1, __bss_end 68*10465441SEvalZero_clr_bss_loop: 69*10465441SEvalZero sw zero, 0(t0) 70*10465441SEvalZero bne t0, t1, _clr_bss_loop 71*10465441SEvalZero addiu t0, t0, 4 72*10465441SEvalZero 73*10465441SEvalZero /* jump to RT-Thread RTOS */ 74*10465441SEvalZero jal rtthread_startup 75*10465441SEvalZero nop 76*10465441SEvalZero 77*10465441SEvalZero /* restart, never die */ 78*10465441SEvalZero j _start 79*10465441SEvalZero nop 80*10465441SEvalZero .set reorder 81*10465441SEvalZero 82*10465441SEvalZero .globl cp0_get_cause 83*10465441SEvalZerocp0_get_cause: 84*10465441SEvalZero mfc0 v0, CP0_CAUSE 85*10465441SEvalZero jr ra 86*10465441SEvalZero nop 87*10465441SEvalZero 88*10465441SEvalZero .globl cp0_get_status 89*10465441SEvalZerocp0_get_status: 90*10465441SEvalZero mfc0 v0, CP0_STATUS 91*10465441SEvalZero jr ra 92*10465441SEvalZero nop 93*10465441SEvalZero 94*10465441SEvalZero .globl cp0_get_hi 95*10465441SEvalZerocp0_get_hi: 96*10465441SEvalZero mfhi v0 97*10465441SEvalZero jr ra 98*10465441SEvalZero nop 99*10465441SEvalZero 100*10465441SEvalZero .globl cp0_get_lo 101*10465441SEvalZerocp0_get_lo: 102*10465441SEvalZero mflo v0 103*10465441SEvalZero jr ra 104*10465441SEvalZero nop 105*10465441SEvalZero 106*10465441SEvalZero .extern tlb_refill_handler 107*10465441SEvalZero .extern cache_error_handler 108*10465441SEvalZero 109*10465441SEvalZero /* Exception Handler */ 110*10465441SEvalZero /* 0x0 - TLB refill handler */ 111*10465441SEvalZero .section .vectors.1, "ax", %progbits 112*10465441SEvalZero j tlb_refill_handler 113*10465441SEvalZero nop 114*10465441SEvalZero 115*10465441SEvalZero /* 0x100 - Cache error handler */ 116*10465441SEvalZero .section .vectors.2, "ax", %progbits 117*10465441SEvalZero j cache_error_handler 118*10465441SEvalZero nop 119*10465441SEvalZero 120*10465441SEvalZero /* 0x180 - Exception/Interrupt handler */ 121*10465441SEvalZero .section .vectors.3, "ax", %progbits 122*10465441SEvalZero j _general_exception_handler 123*10465441SEvalZero nop 124*10465441SEvalZero 125*10465441SEvalZero /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ 126*10465441SEvalZero .section .vectors.4, "ax", %progbits 127*10465441SEvalZero j _irq_handler 128*10465441SEvalZero nop 129*10465441SEvalZero 130*10465441SEvalZero .section .vectors, "ax", %progbits 131*10465441SEvalZero .extern mips_irq_handle 132*10465441SEvalZero 133*10465441SEvalZero /* general exception handler */ 134*10465441SEvalZero_general_exception_handler: 135*10465441SEvalZero .set noreorder 136*10465441SEvalZero mfc0 k1, CP0_CAUSE 137*10465441SEvalZero andi k1, k1, 0x7c 138*10465441SEvalZero srl k1, k1, 2 139*10465441SEvalZero lw k0, sys_exception_handlers(k1) 140*10465441SEvalZero jr k0 141*10465441SEvalZero nop 142*10465441SEvalZero .set reorder 143*10465441SEvalZero 144*10465441SEvalZero /* interrupt handler */ 145*10465441SEvalZero_irq_handler: 146*10465441SEvalZero .set noreorder 147*10465441SEvalZero la k0, mips_irq_handle 148*10465441SEvalZero jr k0 149*10465441SEvalZero nop 150*10465441SEvalZero .set reorder 151