1/* 2 * File : start_gcc.S 3 * Change Logs: 4 * Date Author Notes 5 * 2010-05-17 swkyer first version 6 * 2010-09-04 bernard porting to Jz47xx 7 */ 8 9#include "../common/mips.inc" 10#include "../common/stackframe.h" 11#include "stack.h" 12 13 .section ".start", "ax" 14 .set noreorder 15 16 /* the program entry */ 17 .globl _start 18_start: 19 .set noreorder 20 la ra, _start 21 22 li t1, 0x00800000 23 mtc0 t1, CP0_CAUSE 24 25 /* init cp0 registers. */ 26 li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ 27 mtc0 t0, CP0_STATUS 28 29 /* setup stack pointer */ 30 li sp, SYSTEM_STACK 31 la gp, _gp 32 33 /* init caches, assumes a 4way * 128set * 32byte I/D cache */ 34 mtc0 zero, CP0_TAGLO /* TAGLO reg */ 35 mtc0 zero, CP0_TAGHI /* TAGHI reg */ 36 li t0, 3 /* enable cache for kseg0 accesses */ 37 mtc0 t0, CP0_CONFIG /* CONFIG reg */ 38 la t0, 0x80000000 /* an idx op should use an unmappable address */ 39 ori t1, t0, 0x4000 /* 16kB cache */ 40 41_cache_loop: 42 cache 0x8, 0(t0) /* index store icache tag */ 43 cache 0x9, 0(t0) /* index store dcache tag */ 44 bne t0, t1, _cache_loop 45 addiu t0, t0, 0x20 /* 32 bytes per cache line */ 46 nop 47 48 /* invalidate BTB */ 49 mfc0 t0, CP0_CONFIG 50 nop 51 ori t0, 2 52 mtc0 t0, CP0_CONFIG 53 nop 54 55 /* copy IRAM section */ 56 la t0, _iramcopy 57 la t1, _iramstart 58 la t2, _iramend 59_iram_loop: 60 lw t3, 0(t0) 61 sw t3, 0(t1) 62 addiu t1, 4 63 bne t1, t2, _iram_loop 64 addiu t0, 4 65 /* clear bss */ 66 la t0, __bss_start 67 la t1, __bss_end 68_clr_bss_loop: 69 sw zero, 0(t0) 70 bne t0, t1, _clr_bss_loop 71 addiu t0, t0, 4 72 73 /* jump to RT-Thread RTOS */ 74 jal rtthread_startup 75 nop 76 77 /* restart, never die */ 78 j _start 79 nop 80 .set reorder 81 82 .globl cp0_get_cause 83cp0_get_cause: 84 mfc0 v0, CP0_CAUSE 85 jr ra 86 nop 87 88 .globl cp0_get_status 89cp0_get_status: 90 mfc0 v0, CP0_STATUS 91 jr ra 92 nop 93 94 .globl cp0_get_hi 95cp0_get_hi: 96 mfhi v0 97 jr ra 98 nop 99 100 .globl cp0_get_lo 101cp0_get_lo: 102 mflo v0 103 jr ra 104 nop 105 106 .extern tlb_refill_handler 107 .extern cache_error_handler 108 109 /* Exception Handler */ 110 /* 0x0 - TLB refill handler */ 111 .section .vectors.1, "ax", %progbits 112 j tlb_refill_handler 113 nop 114 115 /* 0x100 - Cache error handler */ 116 .section .vectors.2, "ax", %progbits 117 j cache_error_handler 118 nop 119 120 /* 0x180 - Exception/Interrupt handler */ 121 .section .vectors.3, "ax", %progbits 122 j _general_exception_handler 123 nop 124 125 /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ 126 .section .vectors.4, "ax", %progbits 127 j _irq_handler 128 nop 129 130 .section .vectors, "ax", %progbits 131 .extern mips_irq_handle 132 133 /* general exception handler */ 134_general_exception_handler: 135 .set noreorder 136 mfc0 k1, CP0_CAUSE 137 andi k1, k1, 0x7c 138 srl k1, k1, 2 139 lw k0, sys_exception_handlers(k1) 140 jr k0 141 nop 142 .set reorder 143 144 /* interrupt handler */ 145_irq_handler: 146 .set noreorder 147 la k0, mips_irq_handle 148 jr k0 149 nop 150 .set reorder 151