1*10465441SEvalZero/* 2*10465441SEvalZero * File : cache_init.S 3*10465441SEvalZero * Change Logs: 4*10465441SEvalZero * Date Author Notes 5*10465441SEvalZero * 2010-05-17 swkyer first version 6*10465441SEvalZero */ 7*10465441SEvalZero#include "../common/mips.inc" 8*10465441SEvalZero#include "../common/mipsregs.h" 9*10465441SEvalZero#include "../common/stackframe.h" 10*10465441SEvalZero 11*10465441SEvalZero .text 12*10465441SEvalZero .set noreorder 13*10465441SEvalZero 14*10465441SEvalZero .globl cache_init 15*10465441SEvalZero .ent cache_init 16*10465441SEvalZerocache_init: 17*10465441SEvalZero .set noreorder 18*10465441SEvalZero mtc0 zero, CP0_TAGLO 19*10465441SEvalZero move t0, a0 // cache total size 20*10465441SEvalZero move t1, a1 // cache line size 21*10465441SEvalZero li t2, 0x80000000 22*10465441SEvalZero addu t3, t0, t2 23*10465441SEvalZero 24*10465441SEvalZero_cache_init_loop: 25*10465441SEvalZero cache 8, 0(t2) // icache_index_store_tag 26*10465441SEvalZero cache 9, 0(t2) // dcache_index_store_tag 27*10465441SEvalZero addu t2, t1 28*10465441SEvalZero bne t2, t3, _cache_init_loop 29*10465441SEvalZero nop 30*10465441SEvalZero 31*10465441SEvalZero mfc0 t0, CP0_CONFIG 32*10465441SEvalZero li t1, 0x7 33*10465441SEvalZero not t1 34*10465441SEvalZero and t0, t0, t1 35*10465441SEvalZero or t0, 0x3 // cacheable, noncoherent, write-back, write allocate 36*10465441SEvalZero mtc0 t0, CP0_CONFIG 37*10465441SEvalZero 38*10465441SEvalZero jr ra 39*10465441SEvalZero nop 40*10465441SEvalZero 41*10465441SEvalZero .set reorder 42*10465441SEvalZero .end cache_init 43