xref: /nrf52832-nimble/rt-thread/libcpu/mips/xburst/cache.h (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero /*
2*10465441SEvalZero  * File      : cache.h
3*10465441SEvalZero  * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
4*10465441SEvalZero  *
5*10465441SEvalZero  *  This program is free software; you can redistribute it and/or modify
6*10465441SEvalZero  *  it under the terms of the GNU General Public License as published by
7*10465441SEvalZero  *  the Free Software Foundation; either version 2 of the License, or
8*10465441SEvalZero  *  (at your option) any later version.
9*10465441SEvalZero  *
10*10465441SEvalZero  *  This program is distributed in the hope that it will be useful,
11*10465441SEvalZero  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12*10465441SEvalZero  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13*10465441SEvalZero  *  GNU General Public License for more details.
14*10465441SEvalZero  *
15*10465441SEvalZero  *  You should have received a copy of the GNU General Public License along
16*10465441SEvalZero  *  with this program; if not, write to the Free Software Foundation, Inc.,
17*10465441SEvalZero  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18*10465441SEvalZero  *
19*10465441SEvalZero  * Change Logs:
20*10465441SEvalZero  * Date           Author       Notes
21*10465441SEvalZero */
22*10465441SEvalZero 
23*10465441SEvalZero #ifndef __CACHE_H__
24*10465441SEvalZero #define __CACHE_H__
25*10465441SEvalZero 
26*10465441SEvalZero /*
27*10465441SEvalZero  * Cache Operations
28*10465441SEvalZero  */
29*10465441SEvalZero #define Index_Invalidate_I          0x00
30*10465441SEvalZero #define Index_Writeback_Inv_D    0x01
31*10465441SEvalZero #define Index_Invalidate_SI         0x02
32*10465441SEvalZero #define Index_Writeback_Inv_SD  0x03
33*10465441SEvalZero #define Index_Load_Tag_I        0x04
34*10465441SEvalZero #define Index_Load_Tag_D        0x05
35*10465441SEvalZero #define Index_Load_Tag_SI       0x06
36*10465441SEvalZero #define Index_Load_Tag_SD       0x07
37*10465441SEvalZero #define Index_Store_Tag_I       0x08
38*10465441SEvalZero #define Index_Store_Tag_D       0x09
39*10465441SEvalZero #define Index_Store_Tag_SI      0x0A
40*10465441SEvalZero #define Index_Store_Tag_SD      0x0B
41*10465441SEvalZero #define Create_Dirty_Excl_D     0x0d
42*10465441SEvalZero #define Create_Dirty_Excl_SD        0x0f
43*10465441SEvalZero #define Hit_Invalidate_I            0x10
44*10465441SEvalZero #define Hit_Invalidate_D            0x11
45*10465441SEvalZero #define Hit_Invalidate_SI           0x12
46*10465441SEvalZero #define Hit_Invalidate_SD           0x13
47*10465441SEvalZero #define Fill                        0x14
48*10465441SEvalZero #define Hit_Writeback_Inv_D     0x15
49*10465441SEvalZero /* 0x16 is unused */
50*10465441SEvalZero #define Hit_Writeback_Inv_SD        0x17
51*10465441SEvalZero #define Hit_Writeback_I         0x18
52*10465441SEvalZero #define Hit_Writeback_D         0x19
53*10465441SEvalZero /* 0x1a is unused */
54*10465441SEvalZero #define Hit_Writeback_SD            0x1b
55*10465441SEvalZero /* 0x1c is unused */
56*10465441SEvalZero /* 0x1e is unused */
57*10465441SEvalZero #define Hit_Set_Virtual_SI      0x1e
58*10465441SEvalZero #define Hit_Set_Virtual_SD      0x1f
59*10465441SEvalZero 
60*10465441SEvalZero void rt_hw_cache_init(void);
61*10465441SEvalZero 
62*10465441SEvalZero #endif
63