xref: /nrf52832-nimble/rt-thread/libcpu/mips/xburst/cache.h (revision 104654410c56c573564690304ae786df310c91fc)
1 /*
2  * File      : cache.h
3  * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
4  *
5  *  This program is free software; you can redistribute it and/or modify
6  *  it under the terms of the GNU General Public License as published by
7  *  the Free Software Foundation; either version 2 of the License, or
8  *  (at your option) any later version.
9  *
10  *  This program is distributed in the hope that it will be useful,
11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *  GNU General Public License for more details.
14  *
15  *  You should have received a copy of the GNU General Public License along
16  *  with this program; if not, write to the Free Software Foundation, Inc.,
17  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18  *
19  * Change Logs:
20  * Date           Author       Notes
21 */
22 
23 #ifndef __CACHE_H__
24 #define __CACHE_H__
25 
26 /*
27  * Cache Operations
28  */
29 #define Index_Invalidate_I          0x00
30 #define Index_Writeback_Inv_D    0x01
31 #define Index_Invalidate_SI         0x02
32 #define Index_Writeback_Inv_SD  0x03
33 #define Index_Load_Tag_I        0x04
34 #define Index_Load_Tag_D        0x05
35 #define Index_Load_Tag_SI       0x06
36 #define Index_Load_Tag_SD       0x07
37 #define Index_Store_Tag_I       0x08
38 #define Index_Store_Tag_D       0x09
39 #define Index_Store_Tag_SI      0x0A
40 #define Index_Store_Tag_SD      0x0B
41 #define Create_Dirty_Excl_D     0x0d
42 #define Create_Dirty_Excl_SD        0x0f
43 #define Hit_Invalidate_I            0x10
44 #define Hit_Invalidate_D            0x11
45 #define Hit_Invalidate_SI           0x12
46 #define Hit_Invalidate_SD           0x13
47 #define Fill                        0x14
48 #define Hit_Writeback_Inv_D     0x15
49 /* 0x16 is unused */
50 #define Hit_Writeback_Inv_SD        0x17
51 #define Hit_Writeback_I         0x18
52 #define Hit_Writeback_D         0x19
53 /* 0x1a is unused */
54 #define Hit_Writeback_SD            0x1b
55 /* 0x1c is unused */
56 /* 0x1e is unused */
57 #define Hit_Set_Virtual_SI      0x1e
58 #define Hit_Set_Virtual_SD      0x1f
59 
60 void rt_hw_cache_init(void);
61 
62 #endif
63